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product specification high performance 8- bit microcontrollers z8 encore! xp ? f64xx series ps019921-0308 copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com
ps019921-0308 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crimzon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ps019921-0308 z8 encore! xp ? f64xx series product specification iii revision history each instance in the revision hi story table reflects a change to this document from its pre- vious revision. for more details, refer to the corresponding pages or appropriate links given in the table below. date revision level description page number march 2008 21 changed title to z8 en core! xp f64xx series. all february 2008 20 changed z8 encore! xp 64k series flash microcontrollers to z8 encore! xp f64xx series flash microcontrollers. deleted three sentences that mentioned z8r642. removed the 40 pdip package. added zenetsc0100zacg to the end of the ordering information table. changed the flag status to unaffected for bit, bset, and bclr in table 133 on page 246. various december 2007 19 updated zilog logo, di sclaimer section, and implemented style guide. updated table 112 . changed z8 encore! 64k series to z8 encore! xp 64k series flash microcontrollers throughout the document. all december 2006 18 updated table 110 and ordering information . 224 , 265 november 2006 17 updated part number suffix designations . 270
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification iv table of contents manual objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii about this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii intended audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ez8 ? cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification v control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 voltage brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 stop mode recovery using watchdog timer time-out . . . . . . . . . . . . . . . 50 stop mode recovery using a gpio port pin transition halt . . . . . . . . . . 50 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 port a?h address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 port a?h control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 port a?h input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 port a?h output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification vi interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 70 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 71 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 72 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 interrupt port select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer output signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer 0-3 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . 87 timer 0-3 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 88 timer 0-3 control 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 timer 0-3 control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . 95 watchdog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 96 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 watchdog timer reload upper, high and low byte registers . . . . . . . . . . 97 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . 101 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . 102 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . 103 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . 104 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification vii multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . 113 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . 116 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . 124 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 spi clock phase and polarity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 multi-master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 spi control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 spi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 spi diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 spi baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 138 i2c controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification viii architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 software control of i2c transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 master write and read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 address only transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . 144 write transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 address only transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . 146 write transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . 147 read transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 read transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . 150 i2c control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 i2c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 i2c status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 i2c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 i2c baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 156 i2c diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 i2c diagnostic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 direct memory access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 dma0 and dma1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 configuring dma0 and dma1 for data transfer . . . . . . . . . . . . . . . . . . . . 161 dma_adc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 configuring dma_adc for data transfer . . . . . . . . . . . . . . . . . . . . . . . . . 162 dma control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 dmax control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 dmax i/o address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 dmax address high nibble register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 dmax start/current address low byte register . . . . . . . . . . . . . . . . . . . . 166 dmax end address low byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 dma_adc address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 dma_adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 dma status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification ix operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 automatic power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 dma control of the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 timing using the flash frequenc y registers . . . . . . . . . . . . . . . . . . . . . 182 flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . 185 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . 188 option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 flash memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 flash memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification x debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . 205 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 oscillator operation with an exte rnal rc network . . . . . . . . . . . . . . . . . . . . . 209 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . 222 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 general-purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 228 general-purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . 229 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 ez8 ? cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . 237 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
ps019921-0308 table of contents z8 encore! xp ? f64xx series product specification xi ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
ps019921-0308 manual objectives z8 encore! xp ? f64xx series product specification xii manual objectives this product specification provides detailed operating information for the flash devices within zilog?s z8 encore! xp ? f64xx series microcontrol ler (mcu) products. within this document, the z8f642x, z8f482x, z8f322x, z8f242x, and z8f162x devices are referred to collectively as th e z8 encore! xp f64xx series unless specifically stated otherwise. about this manual zilog ? recommends that you read an d understand everything in this manual before setting up and using the product. however, we recognize that there are different styles of learning. therefore, we have designed this produc t specification to be used either as a how to procedural manual or a reference guide to important data. intended audience this document is written for zilog customer s who are experienced at working with micro- controllers, integrated circuits , or printed circuit assemblies. manual conventions the following assumptions and conventions are adopted to provide clarity and ease of use: courier typeface commands, code lines and fragments, bits, eq uations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the courier typeface. where the use of the font is not indicated, as in the index, the name of the entity is presented in upper case. ? example: flags[1] is smrf . hexadecimal values hexadecimal values are de signated by uppercase h suffix and appear in the courier typeface. ? example: r1 is set to f8h. brackets the square brackets, [ ], indicate a register or bus. ? example: for the register r1[7:0 ], r1 is an 8-bit register, r1[7] is the most significant bit, and r1[0] is the least significant bit.
ps019921-0308 manual objectives z8 encore! xp ? f64xx series product specification xiii braces the curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller register s, buses, or individual bits. ? example: the 12-bit register address { 0h , rp[7:4], r1[3:0]} is composed of a 4-bit hexadecimal value ( 0h ) and two 4-bit register values taken from the register pointer (rp) and working register r1. 0h is the most-significant ni bble (4-bit value) of the 12-bit register, and r1[3:0] is the least significant nibble of the 12-bit register. parentheses the parentheses, ( ), indicate an indirect register address lookup. ? example: (r1) is the memory location referenced by th e address contained in the working register r1. parentheses/bracket combinations the parentheses, ( ), indicate an indirect regi ster address lookup and the square brackets, [ ], indicate a register or bus. ? example: assume pc[15:0] contains the value 1234h . (pc[15:0]) then refers to the contents of the memory location at address 1234h . use of the words set , reset and clear the word set implies that a register bit or a cond ition contains a logical 1. the words re set or clear imply that a register bit or a condition co ntains a logical 0. when either of these terms is followed by a number, the word logical may not be included; however, it is implied. notation for bits and similar registers a field of bits within a register is designated as: register[ n : n ]. ? example: addr[15:0] refers to bits 15 through bit 0 of the address. use of the terms lsb , msb , lsb , and msb in this document, the terms lsb and msb, when appearing in upper case, mean least significant byte and most significant byte , respectively. the lowercase forms, lsb and msb , mean least significant bit and most significant bit , respectively. use of initial uppercase letters initial uppercase letters designate settin gs and conditions in general text. ? example 1: the receiver fo rces the scl line to low. ? example 2: the master can generate a stop condition to abort the transfer.
ps019921-0308 manual objectives z8 encore! xp ? f64xx series product specification xiv use of all uppercase letters the use of all uppercase letters designates the names of states, modes, and commands. ? example 1: the bus is considered busy after the start condition. ? example 2: a start command triggers the processing of the initialization sequence. ? example 3: stop mode. bit numbering bits are numbered from 0 to n?1 where n indicates the total number of bits. for example, the 8 bits of a register are numbered from 0 to 7. safeguards it is important that you unde rstand the following safety te rms, which are defined here. indicates a procedure or file may be come corrupted if you do not follow directions. caution:
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 1 introduction zilog?s z8 encore! xp mcu family of products are a line of zilog ? microcontroller products based upon the 8-bit ez8 cpu. the z8 encore! xp ? f64xx series, hereafter referred to collectively as the z8 encore! xp or the f64xx series adds flash memory to zilog?s extensive line of 8-bit microcontr ollers. the flash in-circuit programming capability allows for faster de velopment time and program changes in the field. the new ez8 ? cpu is upward compatible with existing z8 ? instructions. the rich-peripheral set of the z8 encore! xp makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors. features the features of z8 encore ! xp f64xx series include: ? 20 mhz ez8 cpu ? up to 64 kb flash with in-circuit programming capability ? up to 4 kb register ram ? 12-channel, 10-bit analog-to-digital converter (adc) ? two full-duplex 9-bit uarts with bu s transceiver driver enable control ? inter-integrated circuit (i 2 c) ? serial peripheral interface (spi) ? two infrared data association (irda)-c ompliant infrared encoder/decoder s ? up to four 16-bit timers with cap ture, compare, and pwm capability ? watchdog timer (wdt) with internal rc oscillator ? three-channel dma ? up to 60 input/output (i/o) pins ? 24 interrupts with configurable priority ? on-chip debugger ? voltage brownout (vbo) protection ? power-on reset (por) ? operating voltage of 3.0 v to 3.6 v with 5 v-tolerant inputs ? 0 c to +70 c, ?40 c to +105 c, and ?40 c to +125 c operating temperature ranges
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 2 part selection guide table 1 identifies the basic features and package styles available for each device within the z8 encore! xp product line. table 1. z8 encore! xp ? f64xx series part selection guide part number flash (kb) ram (kb) i/o 16-bit timers with pwm adc inputs uarts with irda i 2 cspi 44-pin packages 64/68-pin packages 80-pin package z8f1621 16 2 31 3 8 2 1 1 x z8f1622 16 2 46 4 12 2 1 1 x z8f2421 24 2 31 3 8 2 1 1 x z8f2422 24 2 46 4 12 2 1 1 x z8f3221 32 2 31 3 8 2 1 1 x z8f3222 32 2 46 4 12 2 1 1 x z8f4821 48 4 31 3 8 2 1 1 x z8f4822 48 4 46 4 12 2 1 1 x z8f4823 48 4 60 4 12 2 1 1 x z8f6421 64 4 31 3 8 2 1 1 x z8f6422 64 4 46 4 12 2 1 1 x z8f6423 64 4 60 4 12 2 1 1 x die form sales contact zilog ?
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 3 block diagram figure 1 displays the block diagram of the architecture of the z8 encore! xp ? f64xx series. figure 1. z8 encore! xp ? f64xx series block diagram cpu and peripheral overview ez8 ? cpu features the latest 8-bit ez8 cpu meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 ? instruction set. gpio irda uarts i 2 c timers spi adc flash controller ram ram controller flash interrupt controller on-chip debugger ez8 tm cpu wdt with rc oscillator por/vbo and reset controller xtal/rc oscillator register bus memory busses system clock dma memory
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 4 the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 code ? expanded internal register file allows access of up to 4 kb ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2 to 9 clock cycles per instruction for more information on the ez8 cpu, refer to ez8 ? cpu core user manual (um0128) available for download at www.zilog.com . general-purpose input/output the z8 encore! xp ? f64xx series feature seven 8-bit ports (ports a-g) and one 4-bit port (port h) for general- purpose input/output (gpio). each pin is individually programmable. all ports (except b an d h) support 5 v-tolerant inputs. flash controller the flash controller programs and erases the flash memory. 10-bit analog-to-digital converter the analog-to-digital converter converts an analog input signal to a 10-bit binary number. the adc accepts inputs from up to 12 different analog input sources. uarts each uart is full-duplex and capable of handling asynchronous data transfers. the uarts support 8- and 9-bit data modes, select able parity, and an efficient bus transceiver driver enable signal for controlling a multi-transceiver bus, such as rs-485.
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 5 i 2 c the i 2 c controller makes the z8 encore ! xp compatible with the i 2 c protocol. the i 2 c controller consists of two bidirectional bus lin es, a serial data (sda) line and a serial clock (scl) line. serial peripheral interface the serial peripheral interface allows the z8 encore! xp to exchange data between other peripheral devices such as eeproms, a/d converters and isdn devices. the spi is a full-duplex, synchronous, character-oriented ch annel that supports a four-wire interface. timers up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provide a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, compare, capture and compare, and pwm modes. only 3 timers (timers 0-2) are available in the 44- pin packages. interrupt controller the z8 encore! xp ? f64xx series products support up to 24 interrupts. these interrupts consist of 12 internal and 12 gpio pins. the interrupts have 3 levels of programmable interrupt priority. reset controller the z8 encore! xp can be reset using the reset pin, power-on reset, watchdog timer, stop mode exit, or voltage brownout (vbo) warning signal. on-chip debugger the z8 encore! xp features an integrated on-chip debugger. the ocd provides a rich set of debugging capabilities, such as read ing and writing registers, programming the flash, setting breakpoints and executing co de. a single-pin interface provides communication to the ocd. dma controller the z8 encore! xp ? f64xx series feature three channels of dma. two of the channels are for register ram to and from i/o operatio ns. the third channel au tomatically controls the transfer of data from the adc to the memory.
ps019921-0308 introduction z8 encore! xp ? f64xx series product specification 6
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 7 signal and pin descriptions the z8 encore! xp ? f64xx series product are available in a variety of packages styles and pin configurations. this ch apter describes the signals and available pin configurations for each of the package styles. for informa tion on physical package specifications, see packaging on page 261. available packages table 2 identifies the package styles that are available for each device within the z8 encore! xp f64xx series product line. table 2. z8 encore! xp f64xx series package options part number 44-pin lqfp 44-pin plcc 64-pin lqfp 68-pin plcc 80-pin qfp z8f1621 x x z8f1622 x x z8f2421 x x z8f2422 x x z8f3221 x x z8f3222 x x z8f4821 x x z8f4822 x x z8f4823 x z8f6421 x x z8f6422 x x z8f6423 x
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 8 pin configurations figure 2 through figure 6 on page 12 display the pin configurations for all of the packages available in the z8 encore! xp f64xx seri es. for description of the signals, see table 3 on page 13. timer 3 is not available in the 44-pin packages. figure 2. z8 encore! xp f64 xx series in 44-pin plastic leaded chip carrier (plcc) pa7 / sda pd6 / cts1 pc3 / sck vss vdd vss pc7 / t2out pc6 / t2in dbg pa0 / t0in pd2 pc2 / ss reset vdd vss vdd pd1 pd0 7 39 pc1 / t1out xout pc0 / t1in xin pa1 / t0out pa2 / de0 pa3 / cts0 pc5 / miso pd3 / de1 pd4 / rxd1 pd5 / txd1 pc4 / mosi pa4 / rxd0 pa5 / txd0 pa6 / scl avdd pb6 / ana6 pb5 / ana5 pb0 / ana0 pb1 / ana1 pb4 / ana4 pb7 / ana7 vref pb2 / ana2 pb3 / ana3 avss 640 1 17 29 28 18 12 23 34
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 9 figure 3. z8 encore! xp f64xx series in 44-pin low-profile quad flat package (lqfp) pa7 / sda pd6 / cts1 pc3 / sck vss vdd vss pc7 / t2out pc6 / t2in dbg pa0 / t0in pd2 pc2 / ss reset vdd vss vdd pd1 pd0 34 22 pc1 / t1out xout pc0 / t1in xin pa1 / t0out pa2 / de0 pa3 / cts0 pc5 / miso pd3 / de1 pd4 / rxd1 pd5 / txd1 pc4 / mosi pa4 / rxd0 pa5 / txd0 pa6 / scl avdd pb6 / ana6 pb5 / ana5 pb0 / ana0 pb1 / ana1 pb4 / ana4 pb7 / ana7 vref pb2 / ana2 pb3 / ana3 avss 33 23 44 12 11 1 28 39 17 6
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 10 figure 4. z8 encore! xp f64xx series in 64- pin low-profile quad flat package (lqfp) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout vss pe5 pe6 pe7 vdd pa0 / t0in pd2 pc2 / ss reset vdd pe4 pe3 vss pe2 49 32 pg3 pe1 vdd pe0 pa1 / t0out pa2 / de0 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 ph1 / ana9 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 48 1 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in 17 pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss 16 vss pd1 / t3out pd0 / t3in xout xin 64 pd3 / de1 vdd pa4 / rxd0 pa5 / txd0 pa6 / scl 33 vss 56 40 25 8
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 11 figure 5. z8 encore! xp f64xx series in 68-pin plastic leaded chip carrier (plcc) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout vss pe5 pe6 pe7 vdd pa0 / t0in pd2 pc2 / ss reset vdd pe4 pe3 vss pe2 10 60 pg3 pe1 vdd pe0 pa1 / t0out pa2 / de0 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 9 27 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss vss vdd pd1 / t3out pd0 / t3in xout pd3 / de1 vss pa4 / rxd0 pa5 / txd0 vdd ph1 / ana9 pa6 / scl 61 vss 44 avss 43 xin 26 1 vdd 18 35 52
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 12 figure 6. z8 encore! xp f64xx series in 80-pin quad flat package (qfp) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout pg0 vss pg1 pg2 pe5 pa0 / t0in pd2 pc2 / ss pf6 reset vdd pf5 pf4 pf3 1 64 pe6 pe4 pe7 pe3 pa1 / t0out pa2 / de0 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 80 25 vdd pg3 pg4 pg5 pg6 pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss vss pe2 pe1 pe0 vss pd3 / de1 vdd pa4 / rxd0 pa5 / txd0 pa6 / scl vss ph1 / ana9 65 vdd 40 pf2 pg7 pf1 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in pf0 vdd pd1 / t3out pd0 / t3in xout vss 41 xin 24 5 10 15 20 30 35 45 50 55 60 70 75
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 13 signal descriptions table 3 describes the z8 encore! xp signals. to determine the signals available for the specific package styles, see pin configurations on page 8. table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a-h pa[7:0] i/o port a[7:0]. these pins are used for general-purpose i/o and support 5 v-tolerant inputs. pb[7:0] i/o port b[7:0]. these pins are used for general-purpose i/o. pc[7:0] i/o port c[7:0]. these pins are used for general-purpose i/o. these pins are used for general-purpose i/o and support 5 v-tolerant inputs pd[7:0] i/o port d[7:0]. these pins are used for general-purpose i/o. these pins are used for general-purpose i/o and support 5 v-tolerant inputs pe[7:0] i/o port e[7:0]. these pins are used for general-purpose i/o. these pins are used for general-purpose i/o and support 5 v-tolerant inputs. pf[7:0] i/o port f[7:0]. these pins are used for general-purpose i/o. these pins are used for general-purpose i/o and support 5 v-tolerant inputs. pg[7:0] i/o port g[7:0]. these pins are used for general-purpose i/o. these pins are used for general-purpose i/o and support 5 v-tolerant inputs. ph[3:0] i/o port h[3:0]. these pins are used for general-purpose i/o. i 2 c controller scl o serial clock. this is the output clock for the i 2 c. this pin is multiplexed with a general-purpose i/o pin. when the general-purpose i/o pin is configured for alternate function to enable the sc l function, this pin is open-drain. sda i/o serial data. this open-drain pin transfers data between the i 2 c and a slave. this pin is multiplexed with a general-purpose i/o pin. when the general-purpose i/o pin is configured for alternate function to enable the sda function, this pin is open-drain. spi controller ss i/o slave select. this signal can be an output or an input. if the z8 encore! xp f64xx series is the spi master, this pin may be configured as the slave select output. if the z8 encore! xp f64xx series is the spi slave, this pin is the input slave select. it is multiplexed with a general-purpose i/o pin.
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 14 sck i/o spi serial clock. the spi master supplies this pin. if the z8 encore! xp f64xx series is the spi master, this pin is an output. if the z8 encore! xp f64xx series is the spi slave, this pin is an input. it is multiplexed with a general-purpose i/o pin. mosi i/o master-out/slave-in. this signal is the data output from the spi master device and the data input to the spi sl ave device. it is multiplexed with a general-purpose i/o pin. miso i/o master-in/slave-out. this pin is the data input to the spi master device and the data output from the spi slave device. it is multiplexed with a general-purpose i/o pin. uart controllers txd0 / txd1 o transmit data. these signals are the transmit outputs from the uarts. the txd signals are multiplexed with general-purpose i/o pins. rxd0 / rxd1 i receive data. these signals are the receiver inputs for the uarts and irdas. the rxd signals are multiplexed with general-purpose i/o pins. cts0 / cts1 i clear to send. these signals are control inputs for the uarts. the cts signals are multiplexed with general-purpose i/o pins. de0 / de1 o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximately the inverse of the transmit empty (txe) bit in the uart status 0 register. the de signal may be used to ensure an external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out/ t2out/t3out o timer output 0-3. these signals are ou tput pins from the timers. the timer output signals are multiplexed with general-purpose i/o pins. t3out is not available in 44-pin package devices. t0in/t1in/ t2in/t3in i timer input 0-3. these signals are us ed as the capture, gating and counter inputs. the timer input signals are multiplexed with general-purpose i/o pins. t3in is not available in 44-pin package devices. analog ana[11:0] i analog input. these signals are inputs to the adc. the adc analog inputs are multiplexed with general-purpose i/o pins. vref i analog-to-digital converter reference voltage input. the vref pin must be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is selected as the adc reference voltage. oscillators table 3. signal descriptions (continued) signal mnemonic i/o description
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 15 pin characteristics table 4 on page 16 provides deta iled information on the characteristics for each pin available on the z8 encore ! xp f64xx series products and the data is sorted alphabetically by the pin symbol mnemonic. xin i external crystal input. this is the in put pin to the crystal oscillator. a crystal can be connected between it and the xout pin to form the oscillator. this signal is usable with external rc ne tworks and an external clock driver. xout o external crystal output. this pin is the output of the crystal oscillator. a crystal can be connected between it and the xin pi n to form the oscillator. when the system clock is referred to in this manual, it refers to the frequency of the signal at this pin. this pin must be left unconnected when not using a crystal. rcout o rc oscillator output. this signal is the output of the rc oscillator. it is multiplexed with a general-purpose i/o pin. this signal must be left unconnected when not using a crystal. on-chip debugger dbg i/o debug. this pin is the control and data input and output to and from the on- chip debugger. this pin is open-drain. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must have an external pull-up resistor to ensure proper operation. reset reset i reset. generates a reset wh en asserted (driven low). power supply vdd i power supply. avdd i analog power supply. vss i ground. avss i analog ground. table 3. signal descriptions (continued) signal mnemonic i/o description caution:
ps019921-0308 signal and pin descriptions z8 encore! xp ? f64xx series product specification 16 table 4. pin characteristics of the z8 encore! xp f64xx series symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt- trigger input open drain output avss n/a n/a n/a n/a no no n/a avdd n/a n/a n/a n/a no no n/a dbg i/o i n/a yes no yes yes vss n/a n/a n/a n/a no no n/a pa[7:0] i/o i n/a yes no yes yes, programmable pb[7:0] i/o i n/a yes no yes yes, programmable pc[7:0] i/o i n/a yes no yes yes, programmable pd[7:0] i/o i n/a yes no yes yes, programmable pe7:0] i/o i n/a yes no yes yes, programmable pf[7:0] i/o i n/a yes no yes yes, programmable pg[7:0] i/o i n/a yes no yes yes, programmable ph[3:0] i/o i n/a yes no yes yes, programmable reset i i low n/a pull-up yes n/a vdd n/a n/a n/a n/a no no n/a xin i i n/a n/a no no n/a xout o o n/a yes, in stop mode no no no note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.
ps019921-0308 address space z8 encore! xp ? f64xx series product specification 17 address space the ez8 ? cpu can access three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and general- purpose i/o port control registers. ? the program memory contains addresses for all memory locations having executable code and/or data. ? the data memory consists of the addresses for all memory locations that hold only data. these three address spaces are covered brie fly in the following subsections. for more information on ez8 cpu and its address space, refer to ez8 ? cpu core user manual (um0128) available for download at www.zilog.com . register file the register file address space in the z8 en core! xp f64xx series is 4 kb (4096 bytes). the register file is composed of two sections?control regi sters and general-purpose reg- isters. when instructions are executed, registers are read from when defined as sources and written to when defined as destinations. the architecture of th e ez8 cpu allows all general-purpose registers to function as accumu lators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256-byte control register section are reserved (unavailable). reading from an reserved register file addresses returns an undefined value. writing to reserved register file addresses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 00 0h in the register file address space. the z8 encore! xp f64xx series provide 2 kb to 4 kb of on-chip ram depending upon the device. reading from register file addresses outside the available ram addresses (and not within the control register address space) returns an unde fined value. writing to these register file addresses produces no effect. to determine the amount of ram available for the specific z8 encore! xp f64xx series device, see part selection guide on page 2. program memory the ez8 ? cpu supports 64 kb of program memo ry address space. the z8 encore! xp f64xx series contains 16 kb to 64 kb of on-chip flash in the program memory address space, depending upon the device. reading from program memory addresses outside the
ps019921-0308 address space z8 encore! xp ? f64xx series product specification 18 available flash memory addresses returns ffh . writing to these unimplemented program memory addresses produces no effect. table 5 describes the program memory maps for the z8 encore! xp f64xx series products. table 5. z8 encore! xp f64xx series program memory maps program memory address (hex) function z8f162x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-3fff program memory z8f242x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-5fff program memory z8f322x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-7fff program memory z8f482x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap
ps019921-0308 address space z8 encore! xp ? f64xx series product specification 19 data memory the z8 encore! xp f64xx series does no t use the ez8 cpu?s 64 kb data memory address space. information area table 6 on page 20 describes the z8 encore! xp f64xx series information area. this 512 byte information area is accessed by setting bit 7 of the page select register to 1. when access is enabled, the information ar ea is mapped into the program memory and overlays the 512 bytes at addresses fe00h to ffffh . when the information area access is enabled, execution of ldc and ldci instru ction from these program memory addresses return the information area data rather th an the program memory data. reads of these addresses through the on-chip debugger al so returns the information area data. execution of code from these addresses conti nues to correctly use the program memory. access to the information area is read-only. 0008-0037 interrupt vectors* 0038-bfff program memory z8f642x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-ffff program memory *see ta b l e 2 3 on page 63 for a list of the interrupt vectors. table 5. z8 encore! xp f64xx series program memory maps (continued) program memory address (hex) function
ps019921-0308 address space z8 encore! xp ? f64xx series product specification 20 table 6. z8 encore! xp f64xx series information area map program memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros (ascii null character) fe54h-ffffh reserved
z8 encore! xp ? f64xx series product specification ps019921-0308 register file address map 21 register file address map table 7 provides the address map for the regist er file of the z8 encore! xp f64xx series products. not all devices and package styles in the z8 en core! xp f64xx series support timer 3 and all of the gpio ports. co nsider registers for unimplemented peripher- als as reserved. table 7. z8 encore! xp f64xx series register file address map address (hex) register description mnemonic reset (hex) page no general-purpose ram 000-eff general-purpose register file ram ? xx timer 0 f00 timer 0 high byte t0h 00 86 f01 timer 0 low byte t0l 01 86 f02 timer 0 reload high byte t0rh ff 87 f03 timer 0 reload low byte t0rl ff 87 f04 timer 0 pwm high byte t0pwmh 00 88 f05 timer 0 pwm low byte t0pwml 00 88 f06 timer 0 control 0 t0ctl0 00 89 f07 timer 0 control 1 t0ctl1 00 90 timer 1 f08 timer 1 high byte t1h 00 86 f09 timer 1 low byte t1l 01 86 f0a timer 1 reload high byte t1rh ff 87 f0b timer 1 reload low byte t1rl ff 87 f0c timer 1 pwm high byte t1pwmh 00 88 f0d timer 1 pwm low byte t1pwml 00 88 f0e timer 1 control 0 t1ctl0 00 89 f0f timer 1 control 1 t1ctl1 00 90 timer 2 f10 timer 2 high byte t2h 00 86 f11 timer 2 low byte t2l 01 86 f12 timer 2 reload high byte t2rh ff 87 f13 timer 2 reload low byte t2rl ff 87 f14 timer 2 pwm high byte t2pwmh 00 88 f15 timer 2 pwm low byte t2pwml 00 88 f16 timer 2 control 0 t2ctl0 00 89
ps019921-0308 register file address map z8 encore! xp ? f64xx series product specification 22 f17 timer 2 control 1 t2ctl1 00 90 timer 3 (unavailable in the 44-pin packages) f18 timer 3 high byte t3h 00 86 f19 timer 3 low byte t3l 01 86 f1a timer 3 reload high byte t3rh ff 87 f1b timer 3 reload low byte t3rl ff 87 f1c timer 3 pwm high byte t3pwmh 00 88 f1d timer 3 pwm low byte t3pwml 00 88 f1e timer 3 control 0 t3ctl0 00 89 f1f timer 3 control 1 t3ctl1 00 90 20-3f reserved ? xx uart 0 f40 uart0 transmit data u0txd xx 110 uart0 receive data u0rxd xx 111 f41 uart0 status 0 u0stat0 0000011xb 111 f42 uart0 control 0 u0ctl0 00 113 f43 uart0 control 1 u0ctl1 00 113 f44 uart0 status 1 u0stat1 00 111 f45 uart0 address compare register u0addr 00 116 f46 uart0 baud rate high byte u0brh ff 116 f47 uart0 baud rate low byte u0brl ff 116 uart 1 f48 uart1 transmit data u1txd xx 110 uart1 receive data u1rxd xx 111 f49 uart1 status 0 u1stat0 0000011xb 111 f4a uart1 control 0 u1ctl0 00 113 f4b uart1 control 1 u1ctl1 00 113 f4c uart1 status 1 u1stat1 00 111 f4d uart1 address compare register u1addr 00 116 f4e uart1 baud rate high byte u1brh ff 116 f4f uart1 baud rate low byte u1brl ff 116 i 2 c f50 i 2 c data i2cdata 00 152 f51 i 2 c status i2cstat 80 153 f52 i 2 c control i2cctl 00 154 f53 i 2 c baud rate high byte i2cbrh ff 156 f54 i 2 c baud rate low byte i2cbrl ff 156 f55 i 2 c diagnostic state i2cdst c0 157 f56 i 2 c diagnostic control i2cdiag 00 159 f57-f5f reserved ? xx serial peripheral interface (spi) table 7. z8 encore! xp f64xx series register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps019921-0308 register file address map z8 encore! xp ? f64xx series product specification 23 f60 spi data spidata xx 133 f61 spi control spictl 00 133 f62 spi status spistat 01 135 f63 spi mode spimode 00 136 f64 spi diagnostic state spidst 00 137 f65 reserved ? xx f66 spi baud rate high byte spibrh ff 138 f67 spi baud rate low byte spibrl ff 138 f68-f6f reserved ? xx analog-to-digital converter f70 adc control adcctl 20 175 f71 reserved ? xx f72 adc data high byte adcd_h xx 176 f73 adc data low bits adcd_l xx 176 f74-faf reserved ? xx dma 0 fb0 dma0 control dma0ctl 00 163 fb1 dma0 i/o address dma0io xx 165 fb2 dma0 end/start address high nibble dma0h xx 165 fb3 dma0 start address low byte dma0start xx 166 fb4 dma0 end address low byte dma0end xx 166 dma 1 fb8 dma1 control dma1ctl 00 163 fb9 dma1 i/o address dma1io xx 165 fba dma1 end/start address high nibble dma1h xx 165 fbb dma1 start address low byte dma1start xx 166 fbc dma1 end address low byte dma1end xx 166 dma adc fbd dma_adc address dmaa_addr xx 167 fbe dma_adc control dmaactl 00 168 fbf dma_adc status dmaastat 00 169 interrupt controller fc0 interrupt request 0 irq0 00 67 fc1 irq0 enable high bit irq0enh 00 70 fc2 irq0 enable low bit irq0enl 00 70 fc3 interrupt request 1 irq1 00 68 fc4 irq1 enable high bit irq1enh 00 71 fc5 irq1 enable low bit irq1enl 00 71 fc6 interrupt request 2 irq2 00 69 fc7 irq2 enable high bit irq2enh 00 72 fc8 irq2 enable low bit irq2enl 00 72 table 7. z8 encore! xp f64xx series register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps019921-0308 register file address map z8 encore! xp ? f64xx series product specification 24 fc9-fcc reserved ? xx fcd interrupt edge select irqes 00 74 fce interrupt port select irqps 00 74 fcf interrupt control irqctl 00 75 gpio port a fd0 port a address paaddr 00 57 fd1 port a control pactl 00 58 fd2 port a input data pain xx 62 fd3 port a output data paout 00 62 gpio port b fd4 port b address pbaddr 00 57 fd5 port b control pbctl 00 58 fd6 port b input data pbin xx 62 fd7 port b output data pbout 00 62 gpio port c fd8 port c address pcaddr 00 57 fd9 port c control pcctl 00 58 fda port c input data pcin xx 62 fdb port c output data pcout 00 62 gpio port d fdc port d address pdaddr 00 57 fdd port d control pdctl 00 58 fde port d input data pdin xx 62 fdf port d output data pdout 00 62 gpio port e fe0 port e address peaddr 00 57 fe1 port e control pectl 00 58 fe2 port e input data pein xx 62 fe3 port e output data peout 00 62 gpio port f fe4 port f address pfaddr 00 57 fe5 port f control pfctl 00 58 fe6 port f input data pfin xx 62 fe7 port f output data pfout 00 62 gpio port g fe8 port g address pgaddr 00 57 fe9 port g control pgctl 00 58 fea port g input data pgin xx 62 feb port g output data pgout 00 62 gpio port h fec port h address phaddr 00 57 fed port h control phctl 00 58 table 7. z8 encore! xp f64xx series register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps019921-0308 register file address map z8 encore! xp ? f64xx series product specification 25 fee port h input data phin xx 62 fef port h output data phout 00 62 watchdog timer ff0 watchdog timer co ntrol wdtctl xxx00000b 96 ff1 watchdog timer reload upper byte wdtu ff 97 ff2 watchdog timer reload high byte wdth ff 97 ff3 watchdog timer reload low byte wdtl ff 97 ff4-ff7 reserved ? xx flash memory controller ff8 flash control fctl 00 186 ff8 flash status fstat 00 186 ff9 page select fps 00 187 ff9 (if enabled) flash sector protect fprot 00 188 ffa flash programming frequency high byte ffreqh 00 188 ffb flash programming frequency low byte ffreql 00 188 ff4-ff8 reserved ? xx read-only memory controller ff9 page select rps 00 ffa-ffb reserved ? xx ez8 cpu ffc flags ? xx refer to ez8 ? cpu core user manual (um0128) ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx note: xx=undefined table 7. z8 encore! xp f64xx series register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 26 control register summary timer 0 high byte t0h (f00h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value [15:8] timer 0 low byte t0l (f01h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value [7:0] timer 0 reload high byte t0rh (f02h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [15:8] timer 0 reload low byte t0rl (hf03 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [7:0] timer 0 pwm high byte t0pwmh (f04h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 pwm value [15:8] timer 0 control 0 t0ctl0 (f06h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 0 input signal is gpio pin 1 = timer 0 input signal is timer 3 out reserved timer 0 control 1 t0ctl1 (f07h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled timer 1 high byte t1h (f08h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value [15:8] timer 1 low byte t1l (f09h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value [7:0] timer 1 reload high byte t1rh (f0ah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [15:8] timer 1 reload low byte t1rl (f0bh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 27 timer 1 pwm high byte t1pwmh (f0ch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [15:8] timer 1 pwm low byte t1pwml (f0dh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [7:0] timer 1 control 0 t1ctl0 (f0eh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 1 input signal is gpio pin 1 = timer 1 input signal is timer 0 out reserved timer 1 control 1 t1ctl1 (f0fh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled timer 2 high byte t2h (f10h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 current count value [15:8] timer 2 low byte t2l (f11h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 current count value [7:0] timer 2 reload high byte t2rh (f12h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 reload value [15:8] timer 2 reload low byte t2rl (f13h- read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 reload value [7:0] timer 2 pwm high byte t2pwmh (f14h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 pwm value [15:8] timer 2 pwm low byte t2pwml (f15h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 2 pwm value [7:0] timer 2 control 0 t2ctl0 (f16h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 2 input signal is gpio pin 1 = timer 2 input signal is timer 1 out reserved
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 28 timer 2 control 1 t2ctl1 (f17h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled timer 3 high byte t3h (f18h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 current count value [15:8] timer 3 low byte t3l (f19h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 current count value [7:0] timer 3 reload high byte t3rh (f1ah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 reload value [15:8] timer 3 reload low byte t3rl (f1bh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 reload value [7:0] timer 3 pwm high byte t3pwmh (f1ch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 pwm value [15:8] timer 3 pwm low byte t3pwml (f1dh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 3 pwm value [7:0] timer 3 control 0 t3ctl0 (f1eh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 3 input signal is gpio pin 1 = timer 3 input signal is timer 2 out reserved timer 3 control 1 t3ctl1 (f1fh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 29 uart0 transmit data u0txd (f40h - write only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 transmitter data byte [7:0] uart0 receive data u0rxd (f40h - read only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 receiver data byte [7:0] uart0 status 0 u0stat0 (f41h - read only) d7 d6 d5 d4 d3 d2 d1 d0 cts signal returns the level of the cts signal transmitter empty 0 = data is currently transmitting 1 = transmission is complete transmitter data register empty 0 = transmit data register is full 1 = transmit data register is empty break detect 0 = no break occurred 1 = a break occurred framing error 0 = no framing error occurred 1 = a framing occurred overrun error 0 = no overrun error occurred 1 = an overrun error occurred parity error 0 = no parity error occurred 1 = a parity error occurred receive data available 0 = receive data register is empty 1 = a byte is available in the receive data register uart0 control 0 u0ctl0 (f42h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 loop back enable 0 = normal operation 1 = transmit data is looped back to the receiver stop bit select 0 = transmitter sends 1 stop bit 1 = transmitter sends 2 stop bits send break 0 = no break is sent 1 = output of the transmitter is zero parity select 0 = even parity 1 = odd parity parity enable 0 = parity is disabled 1 = parity is enabled cts enable 0 = cts signal has no effect on the transmitter 1 = uart recognizes cts signal as a transmit enable control signal receive enable 0 = receiver disabled 1 = receiver enabled transmit enable 0 = transmitter disabled 1 = transmitter enabled
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 30 uart0 control 1 u0ctl1 (f43h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 infrared encoder/decoder enable 0 = infrared endec is disabled 1 = infrared endec is enabled received data interrupt enable 0 = received data and errors generate interrupt requests 1 = only errors generate interrupt requests. received data does not. baud rate registers control refer to uart chapter for operation driver enable polarity 0 = de signal is active high 1 = de signal is active low multiprocessor bit transmit 0 = send a 0 as the multiprocessor bit 1 = send a 1 as the multiprocessor bit multiprocessor mode [0] see multiprocessor mode [1] below multiprocessor (9-bit) enable 0 = multiprocessor mode is disabled 1 = multiprocessor mode is enabled multiprocessor mode [1] with multiprocess mode bit 0: 00 = interrupt on all received bytes 01 = interrupt only on address bytes 10 = interrupt on address match and following data 11 = interrupt on data following an address match uart0 status 1 u0stat1 (f44h - read only) d7 d6 d5 d4 d3 d2 d1 d0 mulitprocessor receive returns value of last multiprocessor bit new frame 0 = current byte is not start of frame 1 = current byte is start of new frame reserved uart0 address compare u0addr (f45h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 address compare [7:0] uart0 baud rate generator high byte u0brh (f46h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor [15:8] uart0 baud rate generator low byte u0brl (f47h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor [7:0] uart1 transmit data u1txd (f48h - write only) d7 d6 d5 d4 d3 d2 d1 d0 uart1 transmitter data byte[7:0] uart1 receive data u1rxd (f48h - read only) d7 d6 d5 d4 d3 d2 d1 d0 uart receiver data byte [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 31 uart1 status 0 u1stat0 (f49h - read only) d7 d6 d5 d4 d3 d2 d1 d0 cts signal returns the level of the cts signal transmitter empty 0 = data is currently transmitting 1 = transmission is complete transmitter data register empty 0 = transmit data register is full 1 = transmit data register is empty break detect 0 = no break occurred 1 = a break occurred framing error 0 = no framing error occurred 1 = a framing occurred overrun error 0 = no overrun error occurred 1 = an overrun error occurred parity error 0 = no parity error occurred 1 = a parity error occurred receive data available 0 = receive data register is empty 1 = a byte is available in the receive data register uart1 control 0 u1ctl0 (f4ah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 loop back enable 0 = normal operation 1 = transmit data is looped back to the receiver stop bit select 0 = transmitter sends 1 stop bit 1 = transmitter sends 2 stop bits send break 0 = no break is sent 1 = output of the transmitter is zero parity select 0 = even parity 1 = odd parity parity enable 0 = parity is disabled 1 = parity is enabled cts enable 0 = cts signal has no effect on the transmitter 1 = uart recognizes cts signal as a transmit enable control signal receive enable 0 = receiver disabled 1 = receiver enabled transmit enable 0 = transmitter disabled 1 = transmitter enabled
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 32 uart1 control 1 u0ctl1 (f4bh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 infrared encoder/decoder enable 0 = infrared endec is disabled 1 = infrared endec is enabled received data interrupt enable 0 = received data and errors generate interrupt requests 1 = only errors generate interrupt requests. received data does not. baud rate registers control refer to uart chapter for operation driver enable polarity 0 = de signal is active high 1 = de signal is active low multiprocessor bit transmit 0 = send a 0 as the multiprocessor bit 1 = send a 1 as the multiprocessor bit multiprocessor mode [0] see multiprocessor mode [1] below multiprocessor (9-bit) enable 0 = multiprocessor mode is disabled 1 = multiprocessor mode is enabled multiprocessor mode [1] with multiprocess mode bit 0: 00 = interrupt on all received bytes 01 = interrupt only on address bytes 10 = interrupt on address match and following data 11 = interrupt on data following an address match uart1 status 1 u0stat1 (f4ch - read only) d7 d6 d5 d4 d3 d2 d1 d0 mulitprocessor receive returns value of last multiprocessor bit new frame 0 = current byte is not start of frame 1 = current byte is start of new frame reserved uart1 address compare u0addr (f4dh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart1 address compare [7:0] uart1 baud rate generator high byte u0brh (f4eh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart1 baud rate divisor [15:8] uart1 baud rate generator low byte u1brl (f4fh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart1 baud rate divisor [7:0] i 2 c data i2cdata (f50h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c data [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 33 i 2 c status i2cstat (f51h - read only) d7 d6 d5 d4 d3 d2 d1 d0 nack interrupt 0 = no action required to service nak 1 = start/stop not set after nak data shift state 0 = data is not being transferred 1 = data is being transferred transmit address state 0 = address is not being transferred 1 = address is being transferred read 0 = write operation 1 = read operation 10-bit address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted acknowledge 0 = acknowledge not transmitted/received 1 = for last byte, acknowledge was transmitted/received receive data register full 0 = i2c has not received data 1 = data register contains received data transmit data register empty 0 = data register is full 1 = data register is empty i 2 c control i2cctl (f52h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c signal filter enable 0 = digital filtering disabled 1 = low-pass digital filters enabled on sda and scl input signals flush data 0 = no effect 1 = clears i2c data register send nak 0 = do not send nak 1 = send nak after next byte received from slave enable tdre interrupts 0 = do not generate an interrupt when the i2c data register is empty 1 = generate an interrupt when the i2c transmit da ta register is empty baud rate generator interrupt 0 = interrupts behave as set by i2c control 1 = brg generates an interrupt when it counts down to zero send stop condition 0 = do not issue stop condition after data transmission is complete 1 = issue stop condition after data transmission is complete send start condition 0 = do not send start condition 1 = send start condition i2c enable 0 = i2c is disabled 1 = i2c is enabled i2c baud rate generator high byte i2cbrh (f53h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [15:8] i2c baud rate generator low byte i2cbrl (f54h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 34 spi data spidata (f60h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi data [7:0] spi control spictl (f61h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi enable 0 = spi disabled 1 = spi enabled master mode enabled 0 = spi configured in slave mode 1 = spi configured in master mode wire-or (open-drain) mode 0 = spi signals not configured for open-drain 1 = spi signals (sck, ss , miso, and mosi) configured for open- drain clock polarity 0 = sck idles low 1 = spi idles high phase select sets the phase relationship of the data to the clock. brg timer interrupt request 0 = brg timer function is disabled 1 = brg time-out interrupt is enabled start an spi interrupt request 0 = no effect 1 = generate an spi interrupt request interrupt request enable 0 = spi interrupt requests are disabled 1 = spi interrupt requests are enabled spi status spistat (f62h - read only) d7 d6 d5 d4 d3 d2 d1 d0 slave select 0 = if slave, ss pin is asserted 1 = if slave, ss pin is not asserted transmit status 0 = no data transmission in progress 1 = data transmission now in progress reserved slave mode transaction abort 0 = no slave mode transaction abort detected 1 = slave mode transaction abort was detected collision 0 = no multi-master collision detected 1 = multi-master collision was detected overrun 0 = no overrun error detected 1 = overrun error was detected interrupt request 0 = no spi interrupt request pending 1 = spi interrupt request is pending spi mode spimode (f63h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 slave select value if master and spimode[1] = 1: 0 = ss pin driven low 1 = ss pin driven high slave select i/o 0 = ss pin configured as an input 1 = ss pin configured as an output (master mode only) number of data bits per character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 35 111 = 7 bits diagnostic mode control 0 = reading from spibrh, spibrl returns reload values 1 = reading from spibrh, spibrl returns current brg count value reserved spi diagnostic state spidst (f64h - read only) d7 d6 d5 d4 d3 d2 d1 d0 spi state transmit clock enable 0 = internal transmit clock enable signal is deasserted 1 = internal transmit clock enable signal is asserted shift clock enable 0 = internal shift clock enable signal is deasserted 1 = internal shift clock enable signal is asserted spi baud rate generator high byte spibrh (f66h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [15:8] spi baud rate generator low byte spibrl (f67h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [7:0] spi mode spimode (f63h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc control adcctl (f70h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 analog input select 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 = ana5 0110 = ana6 0111 = ana7 1000 = ana8 1001 = ana9 1010 = ana10 1011 = ana11 11xx = reserved continuous mode select 0 = single-shot conversion 1 = continuous conversion external vref select 0 = internal voltage reference selected 1 = external voltage reference selected reserved conversion enable 0 = conversion is complete 1 = begin conversion adc data high byte adcd_h (f72h - read only) d7 d6 d5 d4 d3 d2 d1 d0 adc data [9:2] adc data low bits adcd_l (f73h - read only) d7 d6 d5 d4 d3 d2 d1 d0 reserved adc data [1:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 36 dma0 control dma0ctl (fb0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 request trigger source select 000 = timer 0 001 = timer 1 010 = timer 2 011 = timer 3 100 = uart0 received data register contains valid data 101 = uart1 received data register contains valid data 110 = i2c receiver contains valid data 111 = reserved word select 0 = dma transfers 1 byte per request 1 = dma transfers 2 bytes per request dma0 interrupt enable 0 = dma0 does not generate interrupts 1 = dma0 generates an interrupt when end address data is transferred dma0 data transfer direction 0 = register file to peripheral registers 1 = peripheral registers to register file dma0 loop enable 0 = dma disables after end address 1 = dma reloads start address after end address and continues to run dma0 enable 0 = dma0 is disabled 1 = dma0 is enabled dma0 i/o address dma0io (fb1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma0 peripheral register address low byte of on-chip peripheral control registers on register file page fh dma0 address high nibble dma0h (fb2h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma0 start address [11:8] dma0 end address [11:8] dma0 start/current address low byte dma0start (fb3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma0 start address [7:0] dma0 end address low byte dma0end (fb4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma0 end address [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 37 dma1 control dma1ctl (fb8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 request trigger source select 000 = timer 0 001 = timer 1 010 = timer 2 011 = timer 3 100 = uart0 transmit data register is empty 101 = uart1 transmit data register is empty 110 = i2c transmit data register is empty 111 = reserved word select 0 = dma transfers 1 byte per request 1 = dma transfers 2 bytes per request dma1 interrupt enable 0 = dma1 does not generate interrupts 1 = dma1 generates an interrupt when end address data is transferred dma1 data transfer direction 0 = register file to peripheral registers 1 = peripheral registers to register file dma1 loop enable 0 = dma disables after end address 1 = dma reloads start address after end address and continues to run dma1 enable 0 = dma1 is disabled 1 = dma1 is enabled dma1 i/o address dma1io (fb9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma1 peripheral register address low byte of on-chip peripheral control registers on register file page fh dma1 address high nibble dma1h (fbah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma1 start address [11:8] dma1 end address [11:8] dma1 start/current address low byte dma1start (fbbh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma1 start address [7:0] dma1 end address low byte dma1end (fbch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 dma1 end address [7:0] dma_adc address dmaa_addr (fbdh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved dma_adc address
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 38 dma_adc control dmaactl (fbeh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc analog input number 0000 = analog input 0 updated 0001 = analog input 0-1 updated 0010 = analog input 0-2 updated 0011 = analog input 0-3 updated 0100 = analog input 0-4 updated 0101 = analog input 0-5 updated 0100 = analog input 0-6 updated 0101 = analog input 0-7 updated 1000 = analog input 0-8 updated 1001 = analog input 0-9 updated 1010 = analog input 0-10 updated 1011 = analog inputs 0-11 updated 11xx = reserved reserved interrupt request enable 0 = dma_adc does not generate interrupt requests 1 = dma_adc generates interrupt requests after last analog input dma_adc enable 0 = dma_adc is disabled 1 = dma_adc is enabled dma status dmaa_stat (fbfh - read only) d7 d6 d5 d4 d3 d2 d1 d0 dma0 interrupt request indicator 0 = dma0 is not the source of the irq 1 = dma0 is the source of the irq dma1 interrupt request indicator 0 = dma1 is not the source of the irq 1 = dma1 is the source of the irq dma_adc interrupt request 0 = dma_adc is not the source of the irq 1 = dma_adc is the source of the irq reserved current adc analog input identifies the analog input the adc is currently converting interrupt request 0 irq0 (fc0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc interrupt request spi interrupt request i2c interrupt request uart 0 transmitter interrupt uart 0 receiver interrupt request timer 0 interrupt request timer 1 interrupt request timer 2 interrupt request for all of the above peripherals: 0 = peripheral irq is not pending 1 = peripheral irq is awaiting service irq0 enable high bit irq0enh (fc1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable high bit i2c irq enable high bit uart 0 transmitter irq enable uart 0 receiver irq enable high timer 0 irq enable high bit timer 1 irq enable high bit timer 2 irq enable high bit
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 39 irq0 enable low bit irq0enl (fc2h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable low bit i2c irq enable low bit uart 0 transmitter irq enable uart 0 receiver irq enable low timer 0 irq enable low bit timer 1 irq enable low bit timer 2 irq enable low bit interrupt request 1 irq1 (fc3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a or d pin interrupt request 0 = irq from corresponding pin [7:0] is not pending 1 = irq from corresponding pin [7:0] is awaiting service irq1 enable high bit irq1enh (fc4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a or d pin irq enable high bit irq1 enable low bit irq1enl (fc5h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a or d pin irq enable low bit interrupt request 2 irq2 (fc6h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin interrupt request 0 = irq from corresponding pin [3:0] is not pending 1 = irq from corresponding pin [3:0] is awaiting service dma interrupt request uart 1 transmitter interrupt uart 1 receiver interrupt request timer 3 interrupt request for all of the above peripherals: 0 = peripheral irq is not pending 1 = peripheral irq is awaiting service irq2 enable high bit irq2enh (fc7h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable high bit dma irq enable high bit uart 1 transmitter irq enable uart 1 receiver irq enable high timer 3 irq enable high bit irq2 enable low bit irq2enl (fc8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable low bit dma irq enable low bit uart 1 transmitter irq enable uart 1 receiver irq enable low timer 3 irq enable low bit interrupt edge select irqes (fcdh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a or d interrupt edge select 0 = falling edge 1 = rising edge
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 40 interrupt port select irqps (fceh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a or d port pin select [7:0] 0 = port a pin is the interrupt source 1 = port d pin is the interrupt source interrupt control irqctl (fcfh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved interrupt request enable 0 = interrupts are disabled 1 = interrupts are enabled port a address paaddr (fd0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port a control pactl (fd1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a control[7:0] provides access to port sub- registers port a input data pain (fd2h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port a input data [7:0] port a output data paout (fd3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a output data [7:0] port b address pbaddr (fd4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port b control pbctl (fd5h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b control[7:0] provides access to port sub- registers port b input data pbin (fd6h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port b input data [7:0] port b output data pbout (fd7h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b output data [7:0] port c address pcaddr (fd8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 41 port c control pcctl (fd9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c control[7:0] provides access to port sub- registers port c input data pcin (fdah - read only) d7 d6 d5 d4 d3 d2 d1 d0 port c input data [7:0] port c output data pcout (fdbh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c output data [7:0] port d address pdaddr (fdch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port d address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port d control pdctl (fddh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port d control[7:0] provides access to port sub- registers port d input data pdin (fde h- read only) d7 d6 d5 d4 d3 d2 d1 d0 port d input data [7:0] port d output data pdout (fdfh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port d output data [7:0] port e address peaddr (fe0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port e address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port e control pectl (fe1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port e control[7:0] provides access to port sub- registers port e input data pein (fe2h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port e input data [7:0] port e output data peout (fe3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port e output data [7:0] port f address pfaddr (fe4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port f address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 42 port f control pfctl (fe5h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port f control[7:0] provides access to port sub- registers port f input data pfin (fe6h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port f input data [7:0] port f output data pfout (fe7h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port f output data [7:0] port g address pgaddr (fe8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port g address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port g control pgctl (fe9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port g control[7:0] provides access to port sub- registers port g input data pgin (feah - read only) d7 d6 d5 d4 d3 d2 d1 d0 port g input data [7:0] port g output data pgout (febh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port g output data [7:0] port h address phaddr (fech - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port h address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h-ffh = no function port h control phctl (fedh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port h control [3:0] provides access to port sub- registers reserved port h input data phin (feeh - read only) d7 d6 d5 d4 d3 d2 d1 d0 port h input data [3:0] reserved port h output data phout (fefh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port h output data [3:0] reserved
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 43 watchdog timer control wdtctl (ff0h - read only) d7 d6 d5 d4 d3 d2 d1 d0 sm configuration indicator reserved ext 0 = reset not generated by reset pin 1 = reset generated by reset pin wdt 0 = wdt timeout has not occurred 1 = wdt timeout occurred stop 0 = smr has not occurred 1 = smr has occurred por 0 = por has not occurred 1 = por has occurred watchdog timer reload upper byte wdtu (ff1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [23:16] watchdog timer reload middle byte wdth (ff2 h- read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [15:8] watchdog timer reload low byte wdtl (ff3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [7:0] flash control fctl (ff8h - write only) d7 d6 d5 d4 d3 d2 d1 d0 flash command 73h = first unlock command 8ch = second unlock command 95h = page erase command 63h = mass erase command 5eh = flash sector protect reg select flash status fstat (ff8h - read only) d7 d6 d5 d4 d3 d2 d1 d0 flash controller status 00_0000 = flash controller locked 00_0001 = first unlock received 00_0010 = second unlock received 00_0011 = flash controller unlocked 00_0100 = flash sector protect register selected 00_1xxx = programming in progress 01_0xxx = page erase in progress 10_0xxx = mass erase in progress reserved page select fps (ff9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 page select [6:0] identifies the flash memory page for page erase operation. information area enable 0 = information area access is disabled 1 = information area access is enabled flash sector protect fprot (ff9h - read/write to 1?s) d7 d6 d5 d4 d3 d2 d1 d0 flash sector protect [7:0] 0 = sector can be programmed or erased from user code 1 = sector is protected and cannot be programmed or erased from user code flash frequency high byte ffreqh (ffah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [15:8] flash frequency low byte ffreql (ffbh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [7:0]
ps019921-0308 control register summary z8 encore! xp ? f64xx series product specification 44 flags flags (ffc - read/write) d7 d6 d5 d4 d3 d2 d1 d0 f1 - user flag 1 f2 - user flag 2 h - half carry d - decimal adjust v - overflow flag s - sign flag z - zero flag c - carry flag register pointer rp (ffdh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 working register page address working register group address stack pointer high byte sph (ffeh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [15:8] stack pointer low byte spl (fffh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [7:0]
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 45 reset and stop mode recovery the reset controller within the z8 encore! xp f64xx series controls reset and stop mode recovery operation. in typical operat ion, the following events cause a reset to occur: ? power-on reset ? voltage brownout ? watchdog timer time-out (when configured via the wdt_res option bit to initiate a reset) ? external reset pin assertion ? on-chip debugger initiated reset (ocdctl[0] set to 1) when the z8 encore! xp f64xx series devi ces are in stop mode, a stop mode recov- ery is initiated by either of the following: ? watchdog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source ? dbg pin driven low reset types the z8 encore! xp f64xx series provides two different types of reset operation (system reset and stop mode recovery). the type of reset is a function of both the current operat- ing mode of the z8 encore! xp f64xx series devices and the source of the reset. table 8 lists the types of reset and their operating characteristics. table 8. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 ? cpu reset latency (delay) system reset reset (as applic able) reset 66 wdt oscillator cy cles + 16 system clock cycles stop mode recovery unaffected, except wdt_ctl register reset 66 wdt oscillator cycles + 16 system clock cycles
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 46 system reset during a system reset, the z8 encore! xp f64 xx series devices are held in reset for 66 cycles of the watchdog timer oscillator followe d by 16 cycles of the system clock. at the beginning of reset, all gpio pi ns are configured as inputs. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continue to run. the system clock begins operating following the watch dog timer oscillator cycle count. the ez8 cpu and on-chip peripherals remain idle through th e 16 cycles of th e system clock. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other contro l registers (including the stack pointer, register pointer, and flags) and general- purpose ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset vector address. reset sources table 9 lists the reset sources as a function of the operating mode. the text following pro- vides more detailed information on the indivi dual reset sources. a power-on reset/volt- age brownout event always takes priority over all other possible reset sources to ensure a full system reset occurs. table 9. reset sources and resulting reset type operating mode reset source reset type normal or halt modes power-on reset/voltage brownout system reset watchdog timer time-out when configured for reset system reset reset pin assertion system reset on-chip debugger initiated reset (ocdctl[0] set to 1) system reset except the on-chip debugger is unaffected by the reset stop mode power-on reset/voltage brownout system reset reset pin assertion system reset dbg pin driven low system reset
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 47 power-on reset each device in the z8 encore! xp f64xx seri es contains an internal power-on reset cir- cuit. the por circuit monitors the supply voltage and holds th e device in the reset state until the supply voltage reaches a safe operatin g level. after the supply voltage exceeds the por voltage threshold (v por ), the por counter is enabled and counts 66 cycles of the watchdog timer oscillator. after the po r counter times out, the xtal counter is enabled to count a total of 16 system clock pu lses. the devices are held in the reset state until both the por counter and xtal counter ha ve timed out. after the z8 encore! xp f64xx series devices exit the power-on reset state, the ez8 cpu fetches the reset vec- tor. following power-on reset, the por status bit in the watchdog timer control (wdtctl) register is set to 1. figure 7 displays power-on reset operation. for the por threshold voltage (v por ), see electrical characteristics on page 211. figure 7. power-on reset operation voltage brownout reset the devices in the z8 encore! xp f64x x series provide low voltage brownout protection. the vbo circuit senses when the supply voltage drops to an unsafe level vcc = 0.0 v vcc = 3.3 v v por v vbo primary oscillator internal reset signal program execution oscillator start-up xtal wdt clock por counter delay counter delay not to scale
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 48 (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the power-on reset voltage threshold (v por ), the vbo block holds the device in the reset state. after the supply voltage again exceeds the po wer-on reset voltage threshold, the devices progress through a full system reset sequence, as described in the power-on reset section. following power-on reset, the por status bit in the wa tchdog timer control (wdtctl) register is set to 1. figure 8 displays voltage brownout operation. for the vbo and por threshold voltages (v vbo and v por ), see electrical characteristics on page 211. the voltage brownout circuit can be either enabled or disabled during stop mode. oper- ation during stop mode is set by the vbo_ao option bit. for information on configuring vbo_ao , see option bits page 191. figure 8. voltage brownout reset operation watchdog timer reset if the device is in normal or halt mode, th e watchdog timer can in itiate a system reset at time-out if the wdt_res option bit is set to 1. th is capability is the default vcc = 3.3 v v por v vbo internal reset signal program execution program execution voltage brownout vcc = 3.3 v primary oscillator wdt clock xtal por counter delay counter delay
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 49 (unprogrammed) setting of the wdt_res option bit. the wdt status bit in the wdt control register is set to signify that th e reset was initiated by the watchdog timer. external pin reset the reset pin has a schmitt-triggered input, an internal pull-up, an analog filter and a digital filter to reject noise. once the reset pin is asserted for at least 4 system clock cycles, the devices progress through th e system reset sequence. while the reset input pin is asserted low, the z8 encore! xp f64xx series devices continue to be held in the reset state. if the reset pin is held low beyond the syst em reset time-out, the devices exit the reset state immediately following reset pin deassertion. following a system reset initiated by the external reset pin, the ext status bit in the watchdog timer con- trol (wdtctl) register is set to 1. on-chip debugger initiated reset a power-on reset can be initiated usi ng the on-chip debugger by setting the rst bit in the ocd control register. the on-chip debugger block is not reset but the rest of the chip goes through a normal system reset. the rst bit automatically clears during the system reset. following th e system reset the por bit in the wdt control register is set. stop mode recovery stop mode is entered by the ez8 executing a stop instruction. for detailed stop mode information, see low-power modes on page 45. during stop mode recovery, the devices are held in reset for 66 cycles of the watchd og timer oscillator followed by 16 cycles of the system clock. stop mode recovery only affects the contents of the watchdog timer control register. stop mode recovery does not affect any other values in the register file, including the stack pointer, re gister pointer, flags, peripheral control registers, and general-purpose ram. the ez8 ? cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset vector address. following stop mode recovery, the stop bit in the watchdog timer control register is set to 1. table 10 lists the stop mode reco very sources and resulting actions.
ps019921-0308 reset and stop mode recovery z8 encore! xp ? f64xx series product specification 50 stop mode recovery using watchdog timer time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the watchd og timer control register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and the z8 encore! xp f64xx series devices are co nfigured to respond to interrupts, the ez8 cpu services the watchdog timer interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gp io port pin transition halt each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to high) initia tes stop mode recovery. the gpio stop mode recovery signals are filtered to reject pul ses less than 10 ns (typical) in duration. in the watchdog timer control register, the stop bit is set to 1. in stop mode, the gpio port input da ta registers (pxin) are disabled. the port input data registers re cord the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. thus, short puls- es on the port pin can initiate stop mo de recovery without being written to the port input data register or without init iating an interrupt (if enabled for that pin). table 10. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery fo llowed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery caution:
ps019921-0308 low-power modes z8 encore! xp ? f64xx series product specification 51 low-power modes the z8 encore! xp f64xx series products contain power-saving features. the highest level of power reduction is provided by stop mode. the next level of power reduction is provided by the halt mode. stop mode execution of the ez8 ? cpu?s stop instruction places the device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator is stopped; the xi n pin is driven high and the xout pin is driven low. ? system clock is stopped. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? the watchdog timer and its in ternal rc oscillator continue to operate, if enabled for operation during stop mode. ? the voltage brownout protection circuit contin ues to operate, if enabled for operation in stop mode using the associated option bit. ? all other on-chip peripherals are idle. to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd), the voltage brownout protection must be disabled, and the watchdog timer mu st be disabled. the devices can be brought out of stop mode using stop mode recovery. for more information on stop mode recovery, see reset and stop mode recovery on page 45. stop mo de must not be used when drivin g the z8 encore! xp f64xx series devices with an external clock driver source. halt mode execution of the ez8 cpu?s halt instructio n places the device into halt mode. in halt mode, the operating characteristics are: ? primary crystal oscillator is en abled and continues to operate. ? system clock is enabled and continues to operate. ? ez8 cpu is stopped. caution:
ps019921-0308 low-power modes z8 encore! xp ? f64xx series product specification 52 ? program counter stops incrementing. ? watchdog timer?s internal rc os cillator continues to operate. ? the watchdog timer continue s to operate, if enabled. ? all other on-chip peripherals continue to operate. the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brownout reset ? external reset pin assertion to minimize current in halt mode, all gpio pi ns which are configured as inputs must be driven to one of the supply rails (v cc or gnd).
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 53 general-purpose i/o the z8 encore! xp f64xx series products support a maximum of seven 8-bit ports (ports a?g) and one 4-bit port (port h) for general-purpose input/output (gpio) operations. each port consists of control and data regist ers. the gpio control registers are used to determine data direction, op en-drain, output drive current and alternate pin functions. each port pin is individually programmable. all ports (except b and h) support 5 v-toler- ant inputs. gpio port availability by device table 11 lists the port pins available w ith each device and package type. architecture figure 9 displays a simplified block diagram of a gpio port pin. in figure 9 , the ability to accommodate alternate functions and variable port curre nt drive strength are not illus- trated. table 11. port availability by device and package type device packages port a port b port c port d port e port f port g port h z8x1621 44-pin [7:0] [7:0] [7:0] [6:0] - - - - z8 x 1622 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8 x 2421 44-pin [7:0] [7:0] [7:0] [6:0] - - - - z8 x 2422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8 x 3221 44-pin [7:0] [7:0] [7:0] [6:0] - - - - z8 x 3222 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8 x 4821 44-pin [7:0] [7:0] [7:0] [6:0] - - - - z8 x 4822 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8 x 4823 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] z8 x 6421 44-pin [7:0] [7:0] [7:0] [6:0] - - - - z8 x 6422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8 x 6423 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 54 figure 9. gpio port pin block diagram gpio alternate functions many of the gpio port pins can be used as bo th general-purpose i/o and to provide access to on-chip peripheral functions such as th e timers and serial communication devices. the port a?h alternate function sub-registers conf igure these pins for either general-purpose i/o or alternate function operation. when a pin is configured for alte rnate function, control of the port pin direction (input/output) is passed from the port a?h data direction regis- ters to the alternate functio n assigned to this pin. table 12 lists the alternate functions associated with each port pin. d q dq gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 55 table 12. port alternate function mapping port pin mnemonic alternate function description port a pa0 t0in timer 0 input pa1 t0out timer 0 output pa2 de0 uart 0 driver enable pa3 cts0 uart 0 clear to send pa4 rxd0 /i rrx0 uart 0 /i rda 0 receive data pa5 txd0 /i rtx0 uart 0 /i rda 0 transmit data pa6 scl i 2 c clock (automatically open-drain) pa7 sda i 2 c data (automatically open-drain) port b pb0 ana0 adc analog input 0 pb1 ana1 adc analog input 1 pb2 ana2 adc analog input 2 pb3 ana3 adc analog input 3 pb4 ana4 adc analog input 4 pb5 ana5 adc analog input 5 pb6 ana6 adc analog input 6 pb7 ana7 adc analog input 7 port c pc0 t1in timer 1 input pc1 t1out timer 1 output pc2 ss spi slave select pc3 sck spi serial clock pc4 mosi spi master out / slave in pc5 miso spi master in /s lave out pc6 t2in timer 2 in pc7 t2out timer 2 out
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 56 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins may be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupts generate an interrupt when any edge occurs (both rising and falling). for more information on interrupts using the gpio pins, see interrupt controller on page 63. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 13 lists these port registers. use the port a?h address and control registers together to provide access to sub-regist ers for port configuration and control. port d pd0 t3in timer 3 in (unavailable in 44-pin packages) pd1 t3out timer 3 out (unavailable in 44-pin packages) pd2 n/a no alternate function pd3 de1 uart 1 driver enable pd4 rxd1 /i rrx1 uart 1 /i rda 1 receive data pd5 txd1 /i rtx1 uart 1 /i rda 1 transmit data pd6 cts1 uart 1 clear to send pd7 rcout watchdog timer rc oscillator output port e pe[7:0] n/a no alternate functions port f pf[7:0] n/a no alternate functions port g pg[7:0] n/a no alternate functions port h ph0 ana8 adc analog input 8 ph1 ana9 adc analog input 9 ph2 ana10 adc analog input 10 ph3 ana11 adc analog input 11 table 12. port alternate function mapping (continued) port pin mnemonic alternate function description
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 57 port a?h address registers the port a?h address registers select the gp io port functionality accessible through the port a?h control registers. the port a?h address and control registers combine to pro- vide access to all gpio port control ( table 14 ). table 13. gpio port registers and sub-registers port register mnemonic port register name p x addr port a ? h address register (selects sub-registers) p x ctl port a ? h control register (provides access to sub-registers) p x in port a ? h input data register p x out port a ? h output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) pxdd high drive enable p x smre stop mode reco very source enable table 14. port a ? h gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/w addr fd0h, fd4h, fd8h, fdch, fe0h, fe4h, fe8h, fech
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 58 paddr[7:0]?port address the port address selects one of the sub-regi sters accessible through the port control reg- ister. port a?h control registers the port a?h control registers set the gpio port operation. the value in the correspond- ing port a?h address register determines th e control sub-registers accessible using the port a?h control register ( table 15 ). pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. paddr[7:0] port control sub-register accessible using the port a ? h control registers 00h no function. provides some prot ection against accidental port reconfiguration 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop m ode recovery source enable 06h-ffh no function table 15. port a ? h control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/w addr fd1h, fd5h, fd9h, fddh, fe1h, fe5h, fe9h, fedh
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 59 port a ? h data direction sub-registers the port a?h data direction sub-register is accessed through the port a?h control regis- ter by writing 01h to the port a?h address register ( table 16 ). dd[7:0]?data direction these bits control the direction of the associa ted port pin. port alternate function opera- tion overrides the data direction register setting. 0 = output. data in the port a?h output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the value written into the port a?h input data register. the output driver is tri-stated. port a ? h alternate function sub-registers the port a?h alternate fu nction sub-register ( table 17 ) is accessed through the port a?h control register by writing 02h to the port a?h addre ss register. the port a?h alternate function sub-registers select the a lternate functions for the selected pins. to determine the alternate function assoc iated with each port pin, see gpio alternate func- tions on page 54. do not enable alternate fu nction for gpio port pins which do not have an as- sociated alternate function. failure to follow this gu ideline may result in un- predictable operation. table 16. port a ? h data direction sub-registers bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 1 r/w r/w addr if 01h in port a ? h address register, accessible through port a ? h control register table 17. port a ? h alternate function sub-registers bits 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 0 r/w r/w addr if 02h in port a ? h address register, accessible through port a ? h control register caution:
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 60 af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?h data direction sub-register determines the direction of the pin. 1 = the alternate function is selected. po rt pin operation is controlled by the alternate function. port a ? h output control sub-registers the port a?h output control sub-register ( table 18 ) is accessed through the port a?h control register by writing 03h to the port a?h address register. setting the bits in the port a?h output control sub-regist ers to 1 configures th e specified port pins for open-drain oper ation. these sub-registers affect the pins directly and, as a result, alter- nate functions are also affected. poc[7:0]?port output control these bits function independently of the alternate function bit and disables the drains if set to 1. 0 = the drains are enabled for any output mode. 1 = the drain of the associated pin is disabled (open-drain mode). port a ? h high drive enable sub-registers the port a?h high drive enable sub-register ( table 19 ) is accessed through the port a? h control register by writing 04h to the port a?h address register. setting the bits in the port a?h high drive enable sub-registers to 1 configures the specified port pins for high current output drive operation. the port a?h high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. table 18. port a ? h output control sub-registers bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 0 r/w r/w addr if 03h in port a ? h address register, accessible through port a ? h control register
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 61 phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a ? h stop mode recovery source enable sub-registers the port a?h stop mode recovery source enable sub-register ( table 20 ) is accessed through the port a?h cont rol register by writing 05h to the port a?h address register. setting the bits in the port a?h stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mode recovery source . any logic transition on this pin during stop mode initiates stop mode recovery. table 19. port a ? h high drive enable sub-registers bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 0 r/w r/w addr if 04h in port a-h address register, acce ssible through port a-h control register table 20. port a ? h stop mode recovery source enable sub-registers bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 0 r/w r/w addr if 05h in port a ? h address register, accessible through port a ? h control register
ps019921-0308 general-purpose i/o z8 encore! xp ? f64xx series product specification 62 port a?h input data registers reading from the port a?h input data registers ( table 21 ) returns the sampled values from the corresponding port pi ns. the port a?h input data registers are read-only. pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). port a?h output data register the port a?h output data register ( table 22 ) writes output data to the pins. pout[7:0]?port output data these bits contain the data to be driven ou t from the port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alter- nate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is no t driven if the drain has been disabled by setting the corresponding port output control register bit to 1. table 21. port a ? h input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset x r/w r addr fd2h, fd6h, fdah, fdeh, fe2h, fe6h, feah, feeh table 22. port a ? h output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 0 r/w r/w addr fd3h, fd7h, fdbh, fdfh, fe3h, fe7h, febh, fefh
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 63 interrupt controller the interrupt controller on the z8 encore! xp f64xx series products prioritizes the inter- rupt requests from the on-chip peripherals and the gpio port pins. the features of the interrupt controller include the following: ? 24 unique interrupt vectors: ? 12 gpio port pin interrupt sources ? 12 on-chip peripheral interrupt sources ? flexible gpio interrupts ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? three levels of individually programmable interrupt priority ? watchdog timer can be configur ed to generate an interrupt interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, stat us information, or control information between the cpu an d the interrupting peripheral. when the service routine is completed, the cpu returns to the op eration from which it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt control has no effect on oper ation. for more info rmation on interrupt servicing by the ez8 cpu, refer to ez8 ? cpu core user manual (um0128) available for download at www.zilog.com . interrupt vector listing table 23 lists all of the interrupts available in or der of priority. the interrupt vector is stored with the most-significant byte (msb) at the even program memory address and the least-significant byte (lsb) at the following odd program memory address. table 23. interrupt vectors in order of priority priority program memory vector address interrupt source highest 0002h reset (not an interrupt) 0004h watchdog timer (see watchdog timer on page 93) 0006h illegal instruction trap (not an interrupt) 0008h timer 2
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 64 architecture figure 10 displays a block diagram of the interrupt controller. 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h i 2 c 0014h spi 0016h adc 0018h port a7 or port d7, rising or falling input edge 001ah port a6 or port d6, rising or falling input edge 001ch port a5 or port d5, rising or falling input edge 001eh port a4 or port d4, rising or falling input edge 0020h port a3 or port d3, rising or falling input edge 0022h port a2 or port d2, rising or falling input edge 0024h port a1 or port d1, rising or falling input edge 0026h port a0 or port d0, rising or falling input edge 0028h timer 3 (not available in 44-pin packages) 002ah uart 1 receiver 002ch uart 1 transmitter 002eh dma 0030h port c3, both input edges 0032h port c2, both input edges 0034h port c1, both input edges lowest 0036h port c0, both input edges table 23. interrupt vectors in order of priority (continued) (continued) priority program memory vector address interrupt source
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 65 figure 10. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit (irqe) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? executing an enable in terrupt (ei) instruction. ? executing an return from in terrupt (iret) instruction. ? writing a 1 to the irqe bit in the interrupt control register. interrupts are globally disabled by any of the following actions: ? execution of a disable in terrupt (di) instruction. ? ez8 cpu acknowledgement of an interru pt service request from the interrupt controller. ? writing a 0 to the irqe bit in the interrupt control register. ? reset. ? executing a trap instruction. ? illegal instruction trap. vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 66 interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all of the interrupts were enabled with identical interrupt priority (all as level 2 interrupts, for example), then interrupt priority would be assi gned from highest to lowest as specified in table 23 on page 63. level 3 interrupts always have higher priority than level 2 interrupts which, in turn, always have hi gher priority than level 1 inte rrupts. within each interrupt priority level (level 1, level 2, or leve l 3), priority is assigned as specified in table 23 on page 63. reset, watchdog timer interrupt (if en abled), and illegal instruction trap always have highest priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (single pulse). when the interrupt request is acknowledged by the ez8 cpu, the corresponding bit in the interrupt request re gister is cleared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt request register likewise clears the interrupt request. the following style of coding to clear b its in the interrupt request registers is not recommended. all incoming interr upts that are received between execution of the first ldx command an d the last ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 to avoid missing interrupts, the followi ng style of coding to clear bits in the interrupt request 0 register is recommended: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing a 1 to the desired bit in the interrupt request register triggers an interrupt (assumi ng that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. the following style of coding to generate software interrupts by setting bits in the interrupt request registers is not recommended. all incoming interrupts caution: caution:
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 67 that are received between execution of the first ldx command and the last ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, the following style of coding to set bits in the interrupt request registers is recommended: good coding style that avoids lost interrupt requests: orx irq0, mask interrupt control register definitions for all interrupts other than the watchdog ti mer interrupt, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register ( table 24 ) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passes an interrupt request to the ez8 ? cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending t2i?timer 2 interrupt request 0 = no interrupt request is pending for timer 2. 1 = an interrupt request from timer 2 is awaiting service. table 24. interrupt request 0 register (irq0) bits 7 6 5 4 3 2 1 0 field t2i t1i t0i u0rxi u0txi i2ci spii adci reset 0 r/w r/w addr fc0h
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 68 t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. i 2 ci? i 2 c interrupt request 0 = no interrupt request is pending for the i 2 c. 1 = an interrupt request from the i 2 c is awaiting service. spii?spi interrupt request 0 = no interrupt request is pending for the spi. 1 = an interrupt request from the spi is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog-t o-digital converter is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register ( table 25 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. table 25. interrupt request 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pad7i pad6i pad5i pad4i pad3i pad2i pad1i pad0i reset 0 r/w r/w addr fc3h
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 69 pad x i?port a or port d pin x interrupt request 0 = no interrupt request is pendin g for gpio port a or port d pin x . 1 = an interrupt request from gpio port a or port d pin x is awaiting service. where x indicates the specific gpio port pin number (0 through 7). for each pin, only 1 of either port a or port d can be enabled for in terrupts at any one time. port selection (a or d) is determined by th e values in the interrupt port select register. interrupt request 2 register the interrupt request 2 (irq2) register ( table 26 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. t3i?timer 3 interrupt request 0 = no interrupt request is pending for timer 3. 1 = an interrupt request from timer 3 is awaiting service. u1rxi?uart 1 receive interrupt request 0 = no interrupt request is pe nding for the uart1 receiver. 1 = an interrupt request from uart1 receiver is awaiting service. u1txi?uart 1 transmit interrupt request 0 = no interrupt request is pending for the uart 1 transmitter. 1 = an interrupt request from the ua rt 1 transmitter is awaiting service. dmai?dma interrupt request 0 = no interrupt request is pending for the dma. 1 = an interrupt request from the dma is awaiting service. pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. table 26. interrupt request 2 register (irq2) bits 7 6 5 4 3 2 1 0 field t3i u1rxi u1txi dmai pc3i pc2i pc1i pc0i reset 0 r/w r/w addr fc6h
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 70 where x indicates the specific gpio po rt c pin number (0 through 3). irq0 enable high a nd low bit registers the irq0 enable high and low bit registers (see table 28 and table 29 on page 71) form a priority encoded enabling for interrupts in the interrupt requ est 0 register. priority is generated by setting bits in each register. table 27 describes the priority control for irq0. t2enh?timer 2 interrupt re quest enable high bit t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit i2cenh?i 2 c interrupt request enable high bit spienh?spi interrupt request enable high bit adcenh?adc interrupt request enable high bit table 27. irq0 enable and priority encoding irq0enh[ x ]irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: where x indicates the register bits from 0 through 7. table 28. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field t2enh t1enh t0enh u0renh u0tenh i2cenh spienh adcenh reset 0 r/w r/w addr fc1h
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 71 t2enl?timer 2 interrupt request enable low bit t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit i2cenl?i 2 c interrupt request enable low bit spienl?spi interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high a nd low bit registers the irq1 enable high and low bit registers (see table 31 and table 32 on page 72) form a priority encoded enabling for interrupts in the interrupt requ est 1 register. priority is generated by setting bits in each register. table 30 describes the priority control for irq1. table 29. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field t2enl t1enl t0enl u0renl u0tenl i2cenl spienl adcenl reset 0 r/w r/w addr fc2h table 30. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: where x indicates the register bits from 0 through 7.
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 72 pad x enh?port a or port d bit[ x ] interrupt request enable high bit. for selection of either port a or port d as the interrupt source, see interrupt port select register on page 74. pad x enl?port a or port d bit[ x ] interrupt reques t enable low bit for selection of either port a or port d as the interrupt source, see interrupt port select register on page 74. irq2 enable high a nd low bit registers the irq2 enable high and low bit registers (see table 34 and table 35 on page 73) form a priority encoded enabling for interrupts in the interrupt requ est 2 register. priority is generated by setting bits in each register. table 33 describes the priority control for irq2. table 31. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pad7enh pad6enh pad5enh pad4enh pad3enh pad2enh pad1enh pad0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc4h table 32. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pad7enl pad6enl pad5enl pad4enl pad3enl pad2enl pad1enl pad0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc5h table 33. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 73 t3enh?timer 3 interrupt re quest enable high bit u1renh?uart 1 receive interrupt request enable high bit u1tenh?uart 1 transmit interrupt request enable high bit dmaenh?dma interrupt request enable high bit c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit t3enl?timer 3 interrupt request enable low bit u1renl?uart 1 receive interru pt request enable low bit u1tenl?uart 1 transmit interru pt request enable low bit dmaenl?dma interrupt request enable low bit c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit 1 1 level 3 high note: where x indicates the register bits from 0 through 7. table 34. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field t3enh u1renh u1tenh dmaenh c3enh c2enh c1enh c0enh reset 0 r/w r/w addr fc7h table 35. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field t3enl u1renl u1tenl dmaenl c3enl c2enl c1enl c0enl reset 0 r/w r/w addr fc8h table 33. irq2 enable and priority encoding (continued) irq2enh[ x ]irq2enl[ x ] priority description
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 74 c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register ( table 36 ) determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port input pin. the interrupt port select register selects between port a and port d fo r the individual inter- rupts. ies x ?interrupt edge select x the minimum pulse width should be greater than 1 system clock to guarantee capture of the edge triggered interrupt . shorter pulses may be captured but not guaranteed. 0 = an interrupt request is genera ted on the falling edge of the pa x /pd x input. 1 = an interrupt request is genera ted on the rising edge of the pa x /pd x input. where x indicates the specific gpio port pin number (0 through 7). interrupt port select register the port select (irqps) register ( table 37 ) determines the port pin that generates the pax/pdx interrupts. this register allows either port a or port d pins to be used as interrupts. the interrupt edge select regi ster controls the active interrupt edge. table 36. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 0 r/w r/w addr fcdh table 37. interrupt port select register (irqps) bits 7 6 5 4 3 2 1 0 field pad7spad6spad5spad4spad3spad2spad1spad0s reset 0 r/w r/w addr fceh
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 75 pad x s?pa x /pd x selection 0 = pa x is used for the interrupt for pa x /pd x interrupt request. 1 = pd x is used for the interrupt for pa x /pd x interrupt request. where x indicates the specific gpio port pin number (0 through 7). interrupt control register the interrupt control (irqctl) register ( table 38 ) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by execution of an ei or ir et instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executin g a di instruction, ez8 cpu acknowledgement of an interrupt request, or reset. 0 = interrupts are disabled 1 = interrupts are enabled reserved?must be 0. table 38. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 0 r/w r/w r addr fcfh
ps019921-0308 interrupt controller z8 encore! xp ? f64xx series product specification 76
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 77 timers the z8 encore! xp ? f64xx series products contain up to four 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse width modulated sig- nals. the timers? features include: ? 16-bit reload counter ? programmable prescaler with prescale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. ? timer output pin ? timer interrupt in addition to the timers described in this chapter, the baud rate generators for any unused uart, spi, or i 2 c peripherals may also be used to provide basic timing function- ality. for information on using the baud ra te generators as timer s, see the respective serial communication peripheral. timer 3 is unavailable in the 44-pin package devices. architecture figure 11 displays the archit ecture of the timers.
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 78 figure 11. timer block diagram operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001h . then, the timer is automatically disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if it is desired to have the timer output make a permanent state change upon 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer timer block system timer data block interrupt output control bus clock input gate input capture input
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 79 one-shot time-out, first set the tpol bit in the timer control 1 register to the start value before beginning one-shot mode. then, after starting the timer, set tpol to the oppo- site bit value. follow the steps below for configuring a timer for one-shot mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for one-shot mode ? set the prescale value ? if using the timer output alternate functio n, set the initial output level (high or low) 2. write to the timer high and low byte registers to set the starting count value 3. write to the timer reload high and low byte registers to set the reload value 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function 6. write to the timer control 1 register to enable the timer and initiate counting in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) upon timer reload. follow the steps below for configuring a ti mer for continuous mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for continuous mode ? set the prescale value ? if using the timer output alternate functio n, set the initial output level (high or low) one-shot mode time-out period (s) reload value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------ - =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 80 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ), affecting only the first pass in continuous mode. after the first timer reload in continuous mode, counting al ways begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control 1 register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first time-out period. counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio port pi n timer input alternate function. the tpol bit in the timer control 1 register selects whether the co unt occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer input signal must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below for configuring a timer for counter mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for counter mode continuous mode time-out period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ = caution:
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 81 ? select either the rising edge or falling edge of the timer input signal for the count. this also sets the initial logic level (hig h or low) for the timer output alternate function. however, the timer output fu nction does not have to be enabled 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . generally, in counter mode the timer high and low byte registers must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control 1 register to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: pwm mode in pwm mode, the timer output s a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16- bit pwm match value stored in the timer pw m high and low byte registers. when the timer count value matches the pwm value, th e timer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control 1 register is set to 1, the timer output signal begins as a high (1) and then transitions to a lo w (0) when the timer value matches the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control 1 register is set to 0, the timer output signal begins as a low (0) and then transitions to a high (1) when the timer value matches the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . counter mode timer input transiti ons current count value start value ? =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 82 follow the steps below for configuring a timer for pwm mode and initiating the pwm operation: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for pwm mode ? set the prescale value ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control 1 register to enable the timer and initiate counting. the pwm period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first pwm time- out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is given by: if tpol is set to 1, the ratio of the pwm output high time to the total period is given by: capture mode in capture mode, the current timer count valu e is recorded when the desired external timer input transition occurs. the capture coun t value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control 1 register determines if the capture occu rs on a rising edge or a falling edge of the timer input signal. when the capture event occu rs, an interrupt is generated and the timer continues counting. pwm period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value -------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 83 the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt and continues counting. follow the steps below for configuring a timer for capture mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows the software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and lo w byte registers still contain 0000h after the interrupt, then the interrupt was generated by a reload. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control 1 register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon com- pare. if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 84 follow the steps below for configuring a timer for compare mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for compare mode ? set the prescale value ? set the initial logic level (high or low) fo r the timer output alternate function, if desired 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control 1 register to enable the timer and initiate counting. in compare mode, the system clock always pr ovides the timer inpu t. the compare time is given by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control 1 register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal is still asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. follow the steps below for configuring a timer for gated mode and initiating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for gated mode compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ----------------------------------------------------------------------------------------------------- - =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 85 ? set the prescale value 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control 1 register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the desired transition (ri sing edge or falling edge) is set by the tpol bit in the timer control 1 register. the timer input is the system clock. every subsequent desired transitio n (after the first) of the timer input signal captures the current count value. the capture value is wr itten to the timer pwm high and low byte registers. when the capture even t occurs, an interrupt is gene rated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. follow the steps below for configuring a timer for capture/compare mode and initi- ating the count: 1. write to the timer control 1 register to: ? disable the timer ? configure the timer for capture/compare mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function.
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 86 6. write to the timer control 1 register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in m/compare mode, the elapsed time from ti mer start to capture event can be calcu- lated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when th e timer is enabled and the timer high byte register is read, the contents of the time r low byte register are placed in a holding register. a subsequent read from the timer lo w byte register returns the value in the holding register. this operatio n allows accurate reads of th e full 16-bit timer count value while enabled. when the timers are not enabled, a read from the timer low byte register returns the actual va lue in the counter. timer output signal operation timer output is a gpio port pin alternate func tion. generally, the timer output is toggled every time the counter is reloaded. timer control register definitions timers 0-2 are available in all packages. time r 3 is only available in the 64-, 68-, and 80-pin packages. timer 0-3 high and low byte registers the timer 0-3 high and low byte (txh and txl) registers (see table 39 and table 40 on page 87) contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in tx l to be stored in a tempor ary holding register. a read from tmrl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from the tm rl reads the register directly. writing to the timer high and low byte regi sters while the timer is enabled is not recommended. there are no temporary holding registers available for write operations, so simultaneous 16-bit writes are not possible. if e ither the timer high or low byte registers are written during counting, the 8-bit written va lue is placed in the counter (high or low byte) at the next clock edge. the counte r continues counting from the new value. timer 3 is unavailable in the 44-pin packages. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 87 th and tl?timer high and low bytes these 2 bytes, {tmrh[7:0], tmrl[7:0]}, cont ain the current 16-bit timer count value. timer reload high and low byte registers the timer 0-3 reload high and low by te (txrh and txrl) registers (see table 41 and table 42 on page 88) store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stor ed in a temporary holding register. when a write to the timer reload low byte register occurs, the temporary holding register value is written to the timer high byte register. th is operation allows si multaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. table 39. timer 0-3 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 0 r/w r/w addr f00h, f08h, f10h, f18h table 40. timer 0-3 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 01 r/w r/w addr f01h, f09h, f11h, f19h table 41. timer 0-3 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 1 r/w r/w addr f02h, f0ah, f12h, f1ah
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 88 trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count value which in itiates a timer reload to 0001h . in compare mode, these two byte form the 16-bit compare value. timer 0-3 pwm high and low byte registers the timer 0-3 pwm high and low byte (txpwmh and txpwml) registers (see table 43 and table 44 on page 88) are used for puls e-width modulator (pwm) opera- tions. these registers also store the capt ure values for the capture and capture/com- pare modes. table 42. timer 0-3 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 1 r/w r/w addr f03h, f0bh, f13h, f1bh table 43. timer 0-3 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 0 r/w r/w addr f04h, f0ch, f14h, f1ch table 44. timer 0-3 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 0 r/w r/w addr f05h, f0dh, f15h, f1dh
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 89 pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control 1 register (txctl1) regis- ter. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. timer 0-3 control 0 registers the timer 0-3 control 0 (txctl0) registers (see table 45 and table 46 ) allow cascading of the timers. csc?cascade timers 0 = timer input signal comes from the pin. 1 = for timer 0, input signal is connected to timer 3 output. for timer 1, input signal is connected to timer 0 output. for timer 2, input signal is connected to timer 1 output. for timer 3, input signal is connected to timer 2 output. table 45. timer 0-3 control 0 register (txctl0) bits 7 6 5 4 3 2 1 0 field reserved csc reserved reset 0 r/w r/w addr f06h, f0eh, f16h, f1eh
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 90 timer 0-3 control 1 registers the timer 0-3 control 1 (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. table 46. timer 0-3 control 1 register (txctl1) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 0 r/w r/w addr f07h, f0fh, f17h, f1fh
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 91 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first risi ng edge of the timer input signal. the current count is captured on subse quent rising edges of the timer input signal. 1 = counting is started on the first falling edge of the timer input signal. the current count is captured on sub sequent falling edges of the timer input signal. when the timer output alternate func tion txout on a gpio port pin is en- abled, txout will change to whatever state the tpol bit is in. the timer does not need to be enabled for that to happ en. also, the port data direction sub reg- ister is not needed to be set to outp ut on txout. changing the tpol bit with the timer enabled and running does no t immediately change the txout. pres?prescale value. the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this insures proper clock division each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 caution:
ps019921-0308 timers z8 encore! xp ? f64xx series product specification 92 110 = divide by 64 111 = divide by 128 tmode?timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 93 watchdog timer the watchdog timer (wdt) helps protect agai nst corrupt or unreliable software, power faults, and other system-level problems which may place the z8 encore! xp into unsuit- able operating states. the features of watchdog timer include: ? on-chip rc oscillator. ? a selectable time-out response. ? wdt time-out response: reset or interrupt. ? 24-bit programmable time-out value. operation the watchdog timer (wdt) is a retriggerable one-shot timer th at resets or interrupts the z8 encore! xp ? f64xx series devices when the wdt reaches its terminal count. the watchdog timer uses its own dedicated on -chip rc oscillator as its clock source. the watchdog timer has only two modes of operation?on and off. once enabled, it always counts and must be refreshed to prevent a time-out. an enable can be performed by exe- cuting the wdt instruction or by setting the wdt_ao option bit. the wdt_ao bit enables the watchdog timer to operate all th e time, even if a wdt instruction has not been executed. the watchdog timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the ez8 ? cpu register space to set the reload va lue. the nominal wdt time-out period is given by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watchdog timer rc oscillator frequency is 10 khz. the watchdog time r cannot be refreshed once it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 47 provides information on approximate time-out delays for the minimum and maximum wdt reload values. wdt time-out period (ms) wdt reload value 10 ----------------------------------------------- - =
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 94 watchdog timer refresh when first enabled, the watchd og timer is loaded with the value in the watchdog timer reload registers. the watchd og timer then counts down to 000000h unless a wdt instruction is executed by the ez8 ? cpu. execution of the wdt instruction causes the downcounter to be reloaded with the wdt re load value stored in the watchdog timer reload registers. counting resume s following the reload operation. when the z8 encore! xp ? f64xx series devices are operating in debug mode (through the on-chip debugger), the watchd og timer is continuously refreshed to pre- vent spurious watchdog timer time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interrupt or a reset. the wdt_res option bit determines the time-out response of the watchdog timer. fo r information on programming of the wdt_res option bit, see option bits on page 191. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the watchdog timer control register. if interrupts are enable d, the ez8 cpu respon ds to the interrupt request by fetching the watchdog timer inte rrupt vector and executing code from the vector address. after time-out and interrupt ge neration, the watchdog timer counter rolls over to its maximum value of fffffh and continues counting. the watchdog timer counter is not automatically re turned to its reload value. wdt interrupt in stop mode if configured to generate an interrupt when a time-out oc curs and the z8 encore! xp f64xx series devices are in stop mode, the watchdog timer automatically initiates a stop mode recovery and generates an interrupt request. both the wdt status bit and the stop bit in the watchdog timer control regist er are set to 1 following wdt time-out in table 47. watchdog timer approximate time-out delays wdt reload value w dt reload value approximate time-out delay (with 10 khz typical wdt oscillator frequency) (hex) (decimal) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 1677.5 s maximum time-out delay
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 95 stop mode. for more information on stop mode recovery, see reset and stop mode recovery on page 45. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and exe- cuting code from the vector address. wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watchdog timer forces the device into the reset state. the wdt status bit in the watchdog timer control register is set to 1. for more info rmation on reset, see reset and stop mode recovery on page 45. wdt reset in stop mode if enabled in stop mode and configured to ge nerate a reset when a time-out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watchdog timer control register are set to 1 following wdt time-out in stop mode. defa ult operation is for the wdt and its rc oscillator to be enable d during stop mode. wdt rc disable in stop mode to minimize power consumption in stop mode, the wdt and its rc oscillator can be disabled in stop mode. the following sequence configures the wdt to be disabled when the z8 encore! xp ? f64xx series devices enter stop mode following execution of a stop instruction: 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write 81h to the watchdog timer control regist er (wdtctl) to configure the wdt and its oscillator to be disabled duri ng stop mode. alternatively, write 00h to the watchdog timer control register (wdtctl) as the third step in this sequence to reconfigure the wdt and its oscillator to be enabled during stop mode. this sequence only affects wdt operation in stop mode. watchdog timer relo ad unlock sequence writing the unlock sequence to the watchdog timer (wdtctl) control register address unlocks the three watc hdog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. follow th e steps below to unlock the watchdog timer reload byte registers (wdtu, wdth, and wd tl) for write access. 1. write 55h to the watchdog timer control register (wdtctl).
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 96 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu). 4. write the watchdog timer reload high byte register (wdth). 5. write the watchdog timer relo ad low byte register (wdtl). all steps of the watchdog timer reload unlock sequence must be written in the order just listed. there must be no other register writ es between each of these operations. if a regis- ter write occurs, the lock state machine resets and no further writes can occur, unless the sequence is restarted. the value in the watchdog timer reload registers is loaded into the counter when the watchdog timer is first en abled and every time a wdt instruction is executed. watchdog timer control register definitions watchdog timer control register the watchdog timer control (wdtctl) register ( table 48 ) is a read-only register that indicates the source of the most recent reset event, indicates a stop mode recovery event, and indicates a watchdog timer time-out. reading this register resets the upper four bits to 0. writing the 55h , aah unlock sequence to the watchdog timer control (wdtctl) regis- ter address unlocks the three watchdog time r reload byte registers (wdtu, wdth, and wdtl) to allow changes to th e time-out period. these write operations to the wdtctl register address produce no effect on the b its in the wdtctl regist er. the locking mech- anism prevents spurious writ es to the reload registers. table 48. watchdog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved sm reset see descriptions below 0 r/w r addr ff0h
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 97 por?power-on reset indicator if this bit is set to 1, a power-on reset event occurred. this bit is reset to 0 if a wdt time- out or stop mode recovery occurs. this bit is also reset to 0 when the register is read. stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurred. if the stop and wdt bits are both set to 1, the stop mode recovery occurred due to a wd t time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time- out that occurred while not in stop mode. reading this register also resets this bit. wdt?watchdog timer time-out indicator if this bit is set to 1, a wdt time-out occurred. a power-on reset resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register resets this bit. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. reserved these bits are reserved and must be 0. sm?stop mode configuration indicator 0 = watchdog timer and its internal rc oscilla tor will continue to operate in stop mode. 1 = watchdog timer and its internal rc osc illator will be disabled in stop mode. watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, high and low byte (wdtu, wdth, wdtl) regis- ters (see table 49 on page 98 through table 51 on page 98) form the 24-bit reload value that is loaded into the wa tchdog timer when a wdt instruction executes. the 24-bit reload value is {wdtu[7:0], wdth[7:0], wd tl[7:0]}. writing to these registers sets the desired reload value. reading from the se registers returns the current watchdog timer count value. reset or stop mode recovery event por stop wdt ext power-on reset 1 0 0 0 reset using reset pin assertion 0 0 0 1 reset using watchdog timer time-out 0 0 1 0 reset using the on-chip debugger (ocdctl[1] set to 1) 1 0 0 0 reset from stop mode using dbg pin driven low 1 0 0 0 stop mode recovery using gpio pin transition 0 1 0 0 stop mode recovery using watchdog timer time-out 0 1 1 0
ps019921-0308 watchdog timer z8 encore! xp ? f64xx series product specification 98 the 24-bit wdt reload value must not be set to a value less than 000004h . wdtu?wdt reload upper byte most significant byte, bits[23:16], of the 24-bit wdt reload value. wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte, bits[7:0], of the 24-bit wd t reload value. table 49. watchdog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 1 r/w r/w* addr ff1h note: r/w* - read returns the current wdt count value. write sets the desired reload value. table 50. watchdog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 1 r/w r/w* addr ff2h note: r/w* - read returns the current wdt count va lue. write sets the desired reload value. table 51. watchdog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 1 r/w r/w* addr ff3h note: r/w* - read returns the current wdt count value. write sets the desired reload value. caution:
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 99 uart the universal asynchronous receiver/transmitter (uart) is a full-duplex communica- tion channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity. features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode with three config urable interrupt schemes ? baud rate generator timer mode ? driver enable output for external bus transceivers architecture the uart consists of three primary functional blocks: tran smitter, receiver, and baud rate generator. the uart?s transmitter and receiver function indepe ndently, but employ the same baud rate and data format. figure 12 on page 100 displays the uart architec- ture.
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 100 operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be optio nally added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 13 and figure 14 on page 101 displays the asynchronous data format employed by the uart without parity an d with parity, respectively. figure 12. uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 101 transmitting data using the polled method follow the steps below to transmit data using the polled method of operation: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. if multiprocessor mode is desired, wr ite to the uart control 1 register to enable multiprocessor (9-bit) mode functions. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 4. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? if parity is desired and multiprocessor mode is not enable d, set the parity enable bit ( pen ) and select either even or odd parity ( psel ). figure 13. uart asynchronous data format without parity figure 14. uart asynchronous da ta format with parity start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 102 ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. 5. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6 . if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes available to receive new data. 6. write the uart control 1 register to select the outgoing address bit. 7. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 8. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 9. if desired and multiprocessor mode is enabled, make any changes to the multiprocessor bit transmitter (mpbt) value. 10. to transmit additional bytes, return to step 5 . transmitting data using th e interrupt-driven method the uart transmitter inte rrupt indicates the availability of the transmit data register to accept new data for transmission. follow the steps below to configure the uart for inter- rupt-driven data transmission: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the desired priority. 5. if multiprocessor mode is desired, wr ite to the uart control 1 register to enable multiprocessor (9-bit) mode functions. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission. ? enable parity, if desired and if mult iprocessor mode is not enabled, and select either even or odd parity. ? set or clear the ctse bit to enable or disable control from the remote receiver via the cts pin.
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 103 8. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interr upt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine performs the follow- ing: 1. write the uart control 1 register to select the outgoing address bit: ? set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiproc essor mode functions, if desired. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception. ? enable parity, if desired and if mult iprocessor mode is not enabled, and select either even or odd parity. 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 6 . if the receive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the uart receive data register. if operati ng in multiprocessor (9-bit) mode, further actions may be re quired depending on the multiprocessor mode bits mpmd[1:0]. 7. return to step 5 to receive additional data.
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 104 receiving data using the interrupt-driven method the uart receiver interrupt indicates the av ailability of new data (as well as error con- ditions). follow the steps belo w to configure the uart receive r for interrupt-driven oper- ation: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the desired priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if desired. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0], to select the desired address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! xp devices without a dma block). 7. write the device address to the address compare register (aut omatic multiprocessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception. ? enable parity, if desired and if mult iprocessor mode is not enabled, and select either even or odd parity. 9. execute an ei instruction to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associated interrupt service routin e performs the follow- ing: 1. check the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. if the interrupt was caused by data ava ilable, read the data from the uart receive data register. if operating in multipro cessor (9-bit) mode, further actions may be required depending on the multiprocessor mode bits mpmd[1:0] .
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 105 3. clear the uart receiver interrupt in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt -service routine and await more data. clear to send (cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this would typically be done during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9th) bit for selec- tive communication when a number of proce ssors share a common uart bus. in multi- processor mode (also referred to as 9-bit mode), the multiprocessor bit (mp) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as displayed in figure 15 . the character format is: figure 15. uart asynchronous multiprocessor mode data format in multiprocessor (9-bit) mode, the parity bit location (9th bit) becomes the mul- tiprocessor control bit. the uart control 1 and status 1 registers provide multi- processor (9-bit) mode control and status information. if an automatic address matching scheme is enable d, the uart address compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or so me combination of the two, depending on the multiprocessor start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 106 configuration bits. in general, the address co mpare feature reduces the load on the cpu, since it does not need to access the uart when it receives data directed to other devices on the multi-node network. the following three multiprocessor modes are avail- able in hardware: ? interrupt on all address bytes. ? interrupt on matched address bytes and correctly framed data bytes. ? interrupt only on corre ctly framed data bytes. these modes are selected with mpmd[1:0] in the uart control 1 register. for all multiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0] . in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0] . at this point, each new incoming byte interrupts the cp u. the software is then re sponsible for determining the end of the frame. it checks fo r end-of-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, a new frame has begun. if the address of this new frame is different from the uart?s address, then set mpmd[0] to 1 causing the uart interrupts to go inactiv e until the next address byte . if the new frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme is enabled by setting mpmd[1:0] to 10b and writing the uart?s address into the uart address co mpare register. this mode introduces more hardware control, interrupting only on frames that match the uart?s address. when an incoming address byte does not match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte oc curs, an interrupt is issued and further interrupts now occur on each successive data byte. the first data byte in the frame contains the newfrm =1 in the uart status 1 register. when the next address byte occurs, the hardware compares it to the uart? s address. if there is a match, the interrupts continue sand the newfrm bit is set for the first byte of the new frame. if there is no match, then the uart ignores all incomi ng bytes until the next address match. the third scheme is enabled by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame is still accompanied by a newfrm assertion. external driver enable the uart provides a driver enable ( de ) signal for off-chip bus transceivers. this feature reduces the software overhead associated with using a gpio pin to control the transceiver when communicating on a multi-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure 16 . the driver enable signal asserts
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 107 when a byte is written to the uart transmit data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this timing allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the last stop bit is transmit- ted. this one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determ ine if another character follows the current character. in the event of back to back characters (new data must be written to the trans- mit data register before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uart control register 1 sets the polarity of the driver enable signal. figure 16. uart driver enable signal timi ng (shown with 1 stop bit and parity) the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disable d, the baud rate generator can also func- tion as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to accept new data for trans- mission. the tdre interrupt occurs after the transmit sh ift register has shifted the first bit of data out. at this point, the transmit data register may be written with the next character to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ------------------------------------- ?? ?? de to start bit setup time (s) 2 baud rate (hz) ------------------------------------- ?? ?? ?
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 108 receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte has been received and is av ailable in the uart receive data register. this interrupt can be disabled independent of the other receiver interrupt sources. the received data interrupt occu rs once the receive character has been received and placed in the receive data register. software must respond to this re ceived data available condition before the next character is comple tely received to avoid an overrun error. in multiprocessor mode ( mpen = 1), the receive data interrupts are dependent on the multiprocessor configuration a nd the most recent address byte. ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break de tect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain va lid data and should be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 17 on page 109 displays the recommended procedure for use in uart receiver interrupt service routines. note:
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 109 figure 17. uart receiver interrupt service routine flow baud rate generator interrupts if the baud rate generator interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this action allows th e baud rate genera- tor to function as an additional counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate high and low byte registers combine to cr eate a 16-bit baud rate divisor value receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 110 (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate ge nerator can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the desired 16-bit co unt value into the uart baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the brgctl bit in the uart control 1 register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more in formation on the infrared operation, see infrared encoder/decoder on page 121. uart transmit data register data bytes written to the uar t transmit data register ( table 52 ) are shifted out on the txd x pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. table 52. uart transmit data register (u x txd) bits 7 6 5 4 3 2 1 0 field txd reset x r/w w addr f40h and f48h uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------------------------------------------------------------------------------ = interrupt interval s () system clock period (s) brg 15:0 [] =
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 111 txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. uart receive data register data bytes received through the rxd x pin are stored in the uart receive data register ( table 53 ). the read-only uart receive data regi ster shares a register file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart status 0 register the uart status 0 and status 1 registers ( table 54 and table 55 on page 113) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. table 53. uart receive data register (u x rxd) bits 7 6 5 4 3 2 1 0 field rxd reset x r/w r addr f40h and f48h table 54. uart status 0 register (u x stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 01x r/w r addr f41h and f49h
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 112 pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. 0 = no parity error occurred. 1 = a parity error occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, then reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all zeros then this bit is set to 1. reading the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted. txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting. 1 = transmission is complete. cts?cts signal when this bit is read it re turns the level of the cts signal. uart status 1 register this register contains multipro cessor control and status bits.
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 113 reserved?must be 0. newfrm?status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. mprx?multiprocessor receive returns the value of the last multiprocessor bit received. re ading from the uart receive data register resets this bit to 0. uart control 0 and c ontrol 1 registers the uart control 0 and control 1 registers (see table 56 and table 57 on page 114) con- figure the properties of the uart?s transmit and receive op erations. the uart control registers must not been written while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. table 55. uart status 1 register (u x stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 0 r/w rr/wr addr f44h and f4ch table 56. uart control 0 register (u x ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 0 r/w r/w addr f42h and f4ah
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 114 ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. it is over- ridden by the mpen bit. 0 = parity is disabled. 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending da ta before setting this bit. 0 = no break is sent. 1 = the output of the transmitter is zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. mpmd[1:0]?multip rocessor mode if multiprocessor (9-b it) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address). table 57. uart control 1 register (u x ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 0 r/w r/w addr f43h and f4bh
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 115 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt requ est when a received address byte matches the value stored in the addres s compare register and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt requ est on all received data bytes for which the most recent address byte matched the value in the address compare register. mpen?multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiproce ssor (9-bit) mode. mpbt?multiprocessor bit transmit this bit is applicable only when mu ltiprocessor (9-bit) mode is enabled. 0 = send a 0 in the multiprocessor b it location of the data stream (9 th bit). 1 = send a 1 in the multiprocessor b it location of the data stream (9 th bit). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate control this bit causes different uart behavior de pending on whether the uart receiver is enabled ( ren = 1 in the uart control 0 register). when the uart receiver is no t enabled, this bit determines whether the baud rate gener- ator issues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value 1 = the baud rate generator generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enab led, this bit allows reads from the baud rate registers to return the brg count value in stead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and lo w byte registers return the current brg count value. unlike the timers, there is no mechan ism to latch the high byte when the low byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors genera tes an interrupt request to the interrupt controller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled . uart operates normally operation.
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 116 1 = infrared encoder/decoder is enabled. the uart transmits and receives data through the infrared encoder/decoder. uart address compare register the uart address compare register ( table 58 ) stores the multi-node network address of the uart. when the mpmd[1] bit of uart co ntrol register 0 is set, all incoming address bytes are compared to the value stor ed in the address compare register. receive interrupts and rda assertions only occur in the event of a match. comp_addr?compare address this 8-bit value is compared to the incoming address bytes. uart baud rate high and low byte registers the uart baud rate high and low byte registers (see table 59 and table 60 on page 117) combine to create a 16-bit baud rate di visor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. to configure the baud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the desired 16-bit co unt value into the uart baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the brgctl bit in the uart control 1 register to 1. when configured as a general purpose timer, the uart brg interrupt interval is calcu- lated using the following equation: table 58. uart address compare register (u x addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 0 r/w r/w addr f45h and f4dh uart brg interrupt interval s () system clock period (s) brg 15:0 [] =
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 117 for a given uart data rate, the integer baud rate divisor value is calculated using the following equation: the baud rate error relative to the desired baud rate is calculat ed using the following equation: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 61 provides information on data rate erro rs for popular baud rates and commonly used crystal osc illator frequencies. table 59. uart baud rate high byte register (u x brh) bits 7 6 5 4 3 2 1 0 field brh reset 1 r/w r/w addr f46h and f4eh table 60. uart baud rate low byte register (u x brl) bits 7 6 5 4 3 2 1 0 field brl reset 1 r/w r/w addr f47h and f4fh uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ------------------------------------------------------------------------ ?? ?? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------------------------------------------------------------------------------ - ?? ?? =
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 118 table 61. uart baud rates 20.0 mhz system clock 18.432 mhz system clock desired rate brg divi sor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 1 1250.0 0.00 1250.0 1 1152.0 -7.84% 625.0 2 625.0 0.00 625.0 2 576.0 -7.84% 250.0 5 250.0 0.00 250.0 5 230.4 -7.84% 115.2 11 113.6 -1.36 115.2 10 115.2 0.00 57.6 22 56.8 -1.36 57.6 20 57.6 0.00 38.4 33 37.9 -1.36 38.4 30 38.4 0.00 19.2 65 19.2 0.16 19.2 60 19.2 0.00 9.60 130 9.62 0.16 9.60 120 9.60 0.00 4.80 260 4.81 0.16 4.80 240 4.80 0.00 2.40 521 2.40 -0.03 2.40 480 2.40 0.00 1.20 1042 1.20 -0.03 1.20 960 1.20 0.00 0.60 2083 0.60 0.02 0.60 1920 0.60 0.00 0.30 4167 0.30 -0.01 0.30 3840 0.30 0.00 16.667 mhz system clock 11.0592 mhz system clock desired rate brg divi sor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 1 1041.69 -16.67 1250.0 n/a n/a n/a 625.0 2 520.8 -16.67 625.0 1 691.2 10.59 250.0 4 260.4 4.17 250.0 3 230.4 -7.84 115.2 9 115.7 0.47 115.2 6 115.2 0.00 57.6 18 57.87 0.47 57.6 12 57.6 0.00 38.4 27 38.6 0.47 38.4 18 38.4 0.00 19.2 54 19.3 0.47 19.2 36 19.2 0.00 9.60 109 9.56 -0.45 9.60 72 9.60 0.00 4.80 217 4.80 -0.83 4.80 144 4.80 0.00 2.40 434 2.40 0.01 2.40 288 2.40 0.00
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 119 1.20 868 1.20 0.01 1.20 576 1.20 0.00 0.60 1736 0.60 0.01 0.60 1152 0.60 0.00 0.30 3472 0.30 0.01 0.30 2304 0.30 0.00 10.0 mhz system clock 5.5296 mhz system clock desired rate brg divi sor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 3.579545 mhz system clock 1.8432 mhz system clock desired rate brg divi sor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 table 61. uart baud rates (continued)
ps019921-0308 uart z8 encore! xp ? f64xx series product specification 120 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 61. uart baud rates (continued)
ps019921-0308 infrared encoder/decoder z8 encore! xp ? f64xx series product specification 121 infrared encoder/decoder the z8 encore! xp ? f64xx series products contain two fully-functional, high-perfor- mance uart to infrared encoder/decoders (e ndecs). each infrared endec is integrated with an on-chip uart to allow easy co mmunication between the z8 encore! xp ? f64xx series and irda physical layer specification, version 1.3-compliant infrared transceivers. infrared communica tion provides secure, reliable, low-cost, point-to-point communication between pcs, pdas, cell phon es, printers, and ot her infrared enabled devices. architecture figure 18 displays the architecture of the infrared endec. figure 18. infrared data communication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver via the txd pin. likewise, da ta received from the in frared transceiver is passed to the infrared endec via the rxd pin, decoded by the infrared endec, and then passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec) zilog zhx1810
ps019921-0308 infrared encoder/decoder z8 encore! xp ? f64xx series product specification 122 the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enable d to use the infrared endec. the infrared endec data rate is calculated using the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16-clock wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16-clock peri od. if the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. after the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16-clock data period. figure 19 displays irda data transmission. when the infrared endec is enabled, the uart?s txd signal is internal to the z8 encore! xp ? f64xx series products while the ir_txd signal is output through the txd pin. figure 19. infrared data transmission receiving irda data data received from the infrared transceiver via the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared data bit is 16-clocks wide. figure 20 displays data reception. infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------------------------------------------------------------------------------ = baud rate ir_txd uart?s 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3-clock pulse txd clock
ps019921-0308 infrared encoder/decoder z8 encore! xp ? f64xx series product specification 123 when the infrared endec is enab led, the uart?s rxd signal is internal to the z8 encore! xp ? f64xx series products while the ir_rxd signal is received through the rxd pin. figure 20. infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper recep- tion of the 1.6 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected ). this gives the endec a sampling window of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an incoming pulse. if an incoming pulse is dete cted inside this window this process is repeated. if the incoming data is a logical 1 (n o pulse), the endec returns to the initial state and waits for the next falling edge. as eac h falling edge is detected, the endec clock counter is reset, resynchronizing the endec to the incoming signal. this action allows the endec to tolerate jitter and baud rate errors in the incoming data stream. resynchronizing the endec does not alter the operation of th e uart, which ultimately receives the data. the uart is only synchronized to the incoming data stream when a start bit is received. baud rate uart?s ir_rxd 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8-clock delay clock rxd 16-clock period 16-clock period 16-clock period 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.6 s pulse caution:
ps019921-0308 infrared encoder/decoder z8 encore! xp ? f64xx series product specification 124 infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status information is set by the uart control regis- ters as defined in uart control register definitions on page 110. to prevent spurious signals during irda data transmission, set the iren bit in the uartx control 1 register to 1 to enable the infrared encoder/decoder before enabling the gpio port altern ate function for the corresponding pin. caution:
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 125 serial peripheral interface the serial peripheral interface is a synchr onous interface allowi ng several spi-type devices to be interconne cted. spi-compatible devices include eeproms, analog-to- digital converters, and isdn devices. features of the spi include: ? full-duplex, synchronous, character-oriented communication ? four-wire interface ? data transfers rates up to a maximum of one-half the system clock frequency ? error detection ? dedicated baud rate generator architecture the spi may be configured as either a master (in single or multi-master systems) or a slave as displayed in figure 21 through figure 23 . figure 21. spi configured as a master in a single master, single slave system spi master 8-bit shift register bit 0 bit 7 miso mosi sck ss to slave?s ss pin from slave to slave to slave baud rate generator
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 126 figure 22. spi configured as a master in a single master, multiple slave system figure 23. spi configured as a slave operation the spi is a full-duplex, synchronous, characte r-oriented channel that supports a four-wire interface (serial clock, transmit, receive an d slave select). the spi block consists of a transmit/receive shift regist er, a baud rate (clock) ge nerator and a control unit. spi master 8-bit shift register bit 0 bit 7 miso mosi sck gpio to slave #2?s ss pin from slave to slave to slave ss baud rate generator vcc gpio to slave #1?s ss pin spi slave 8-bit shift register bit 7 bit 0 miso mosi sck ss from master to master from master from master
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 127 during an spi transfer, data is sent and recei ved simultaneously by both the master and the slave spi devices. separate signals are requ ired for data and the serial clock. when an spi transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneou sly shifted in on a second data pin. an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular buffer. the spi shift register is single-buffered in th e transmit and receive directions. new data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. spi signals the four basic spi signals are: ? master-in/slave-out ? master-out/slave-in ? serial clock ? slave select each signal is described in both master and slave modes. master-in/slave-out the master-in/slave-out (miso) pin is configur ed as an input in a master device and as an output in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when the sp i is not enabled, this signal is in a high- impedance state. master-out/slave-in the master-out/slave-in (mosi) pin is configured as an output in a master device and as an input in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. when the spi is not enabled, this signal is in a high-impedance state. serial clock the serial clock (sck) synchronizes data movement both in and out of the device through its mosi and miso pins. in master mode, the spi?s baud rate generator cre- ates the serial clock. the master drives the serial clock out its own sck pin to the slave?s sck pin. when the spi is configured as a slav e, the sck pin is an input and the clock sig- nal from the master synchronizes the data tran sfer between the master and slave devices. slave devices ignore the sck signal, unless the ss pin is asserted. when configured as a slave, the spi block requires a minimum sck pe riod of greater than or equal to 8 times the system (xin) clock period.
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 128 the master and slave are each capable of exchanging a character of data during a sequence of numbits clock cycles (see numbits field in the spi mode register on page 136). in both master and slave spi device s, data is shifted on one edge of the sck and is sampled on the opposite edge where data is stable. edge polar ity is determined by the spi phase and polarity control. slave select the active low slave select (ss ) input signal selects a slave spi device. ss must be low prior to all data communication to and from the slave device. ss must stay low for the full duration of each character transferred. the ss signal may stay low during the transfer of multiple characters or may deassert between each character. when the spi is configured as the only master in an spi system, the ss pin can be set as either an input or an output. other gpio output pins can also be employed to select exter- nal spi slave devices. when the spi is configured as one master in a multi-master spi system, the ss pin must be set as an input. the ss input signal on the master must be high. if the ss signal goes low (indicating another master is driving the spi bus), a collis ion error flag is set in the spi status register. spi clock phase and polarity control the spi supports four combinations of serial cl ock phase and polarity using two bits in the spi control register. the clock polarity bit, clkpol , selects an active high or active low clock and has no effect on the transfer format. table 62 lists the spi clock phase and polarity operation parameters. the clock phase bit, phase , selects one of two fundamen- tally different transfer formats. for proper da ta transmission, the clock phase and polarity must be identical for the spi master and the spi slave. the master always places data on the mosi line a half-cycle befo re the receive clock edge (sck signal), in order for the slave to latch the data. table 62. spi clock phase ( phase ) and clock polarity ( clkpol ) operation phase clkpol sck transmit edge sck receive edge sck idle state 0 0 falling rising low 0 1 rising falling high 1 0 rising falling low 1 1 falling rising high
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 129 transfer format phase equals zero figure 24 displays the timing diagram fo r an spi transfer in which phase is cleared to 0. the two sck waveforms show polarity with clkpol reset to 0 and with clkpol set to one. the diagram may be interpreted as either a master or slave timing diagram because the sck master-in/slave-out (m iso) and master-out/slave-in (mosi) pins are directly connected between the master and the slave. figure 24. spi timing when phase is 0 transfer format phase equals one figure 25 on page 130 displays the timing diag ram for an spi transfer in which phase is one. two waveforms are de picted for sck, one for clkpol reset to 0 and another for clkpol set to 1. sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 130 figure 25. spi timing when phase is 1 multi-master operation in a multi-master spi system, all sck pins are tied together, all mosi pins are tied together and all miso pins are tied together. all spi pins must then be configured in open-drain mode to prevent bus contention . at any one time, only one spi device is configured as the master and all other spi de vices on the bus are configured as slaves. the master enables a single slave by asserting the ss pin on that slave only. then, the single master drives data out its sck and mo si pins to the sck and mosi pins on the slaves (including those which are not enable d). the enabled slave drives data out its miso pin to the miso master pin. for a master device operating in a multi-master system, if the ss pin is configured as an input and is driven low by another master, the col bit is set to 1 in the spi status regis- ter. the col bit indicates the occurrence of a multi- master collision (mode fault error con- dition). slave operation the spi block is configured for slave mode operation by setting the spien bit to 1 and the mmen bit to 0 in the spi ctl register and setting the ssi o bit to 0 in the spimode sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 131 register. the irqe, phase, clkpol, wor bits in the spictl register and the num- bits field in the spimode register must be set to be consistent with the other spi devices. the str bit in the spictl register may be used if desired to force a ?startup? interrupt. the birq bit in the spictl register and the ssv bit in the spimode register are not used in slave mode. the spi baud rate generator is not used in slave mode so the spibrh and spibrl registers need not be initialized. if the slave has data to send to the master, th e data must be written to the spidat register before the transaction starts (first edge of sck when ss is asserted). if the spidat register is not written prior to the slave tran saction, the miso pin outputs whatever value is currently in the spidat register. due to the delay resulting from synchronization of the spi input signals to the internal system clock, the maximum spiclk baud rate that can be supported in slave mode is the system clock frequency (xin) divided by 8. this rate is controlled by the spi master. error detection the spi contains error detection logic to support spi communication protocols and recognize when communication errors have o ccurred. the spi status register indicates when a data transmission error has been detected. overrun (write collision) an overrun error (write collisi on) indicates a write to the spi data register was attempted while a data transfer is in progress (in e ither master or slave mo des). an overrun sets the ovr bit in the spi status register to 1. writing a 1 to ovr clears this error flag. the data register is not altered when a write oc curs while data transfer is in progress. mode fault (multi-master collision) a mode fault indicates when mo re than one master is trying to communicate at the same time (a multi-master collision). the mode fault is detected when the enabled master?s ss pin is asserted. a mode fault sets the col bit in the spi status register to 1. writing a 1 to col clears this error flag. slave mode abort in slave mode of operation if the ss pin deasserts before all bits in a character have been transferred, the transaction is aborted. when this condition occurs the abt bit is set in the spistat register as well as the irq bit (indicating the transacti on is complete). the next time ss asserts, the miso pin outputs spidat[7], regardless of where the previous transaction left off. writing a 1 to abt clears this error flag. spi interrupts when spi interrupts are enabled, the spi gene rates an interrupt after character transmis- sion/reception completes in both master and slave modes. a character can be
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 132 defined to be 1 through 8 bits by the numbits field in the spi mode register. in slave mode it is not necessary for ss to deassert between characters to generate the interrupt. the spi in slave mode can also generate an interrupt if the ss signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). writing a 1 to the irq bit in the spi status register clears the pending spi interrupt request. the irq bit must be cleared to 0 by the interrupt service routine to genera te future interrupts. to start the transfer process, an spi interrupt may be forced by software writing a 1 to the str bit in the spictl register. if the spi is disabled, an spi interrupt can be generated by a baud rate generator time- out. this timer function must be enabled by setting the birq bit in the spictl register. this baud rate generator time- out does not set the irq bit in the spistat register, just the spi interrupt bit in the interrupt controller. spi baud rate generator in spi master mode, the baud rate genera tor creates a lower frequency serial clock (sck) for data transmission synchronization between the master and the external slave. the input to the baud rate ge nerator is the system clock. the spi baud rate high and low byte registers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. the spi baud rate is calculated using the following equation: minimum baud rate is obtained by setting brg[15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). when the spi is disabled, the baud rate generator can function as a basic 16-bit timer with interrupt on time-out. follow the steps below to configure the baud rate generator as a timer with interrupt on time-out: 1. disable the spi by clearing the spien bit in the spi control register to 0. 2. load the desired 16-bit co unt value into the spi baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the spi control register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: spi baud rate (bits/s) system clock frequency (hz) 2 brg[15:0] ------------------------------------------------------------------------ = interrupt interval (s) syste m clock period (s) brg[15:0] =
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 133 spi control register definitions spi data register the spi data register ( table 63 ) stores both the outgoing (tra nsmit) data and the incoming (receive) data. reads from the spi data register always return the cu rrent contents of the 8-bit shift register. data is shifted out starting w ith bit 7. the last bit received resides in bit position 0. with the spi configured as a master, writing a da ta byte to this register initiates the data transmission. with the spi conf igured as a slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external master. in either the master or slave modes, if a transmission is already in progress, writes to this register are ignored and the overrun error flag, ovr , is set in the spi status register. when the character length is le ss than 8 bits (as set by the numbits field in the spi mode register), the transmit character must be left justified in the spi data register. a received character of less than 8 bits is right justifie d (last bit received is in bit position 0). for example, if the spi is configured for 4-bit ch aracters, the transmit characters must be writ- ten to spidata[7:4] and the received characters are read from spidata[3:0]. data?data transmit and/or receive data. spi control register the spi control register (see table 64 on page 134) configures the spi for transmit and receive operations. table 63. spi data register (spidata) bits 7 6 5 4 3 2 1 0 field data reset x r/w r/w addr f60h
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 134 irqe?interrupt request enable 0 = spi interrupts are disabled. no interrupt requests are sent to the interrupt controller. 1 = spi interrupts are enabled. interrupt re quests are sent to the interrupt controller. str?start an spi interrupt request 0 = no effect. 1 = setting this bit to 1 also sets the irq bit in the spi status register to 1. setting this bit forces the spi to send an interrupt request to the interrupt control. this bit can be used by software for a functio n similar to transmit buffer empty in a uart. writing a 1 to the irq bit in the spi status register clears this bit to 0. birq?brg timer interrupt request if the spi is enabled, this bit h as no effect. if the spi is disabled: 0 = the baud rate generator timer function is disabled. 1 = the baud rate generator timer func tion and time-out interrupt are enabled. phase?phase select sets the phase relationship of the data to the clock. for more information on operation of the phase bit, see spi clock phase and polarity control on page 128. clkpol?clock polarity 0 = sck idles low (0). 1 = sck idle high (1). wor?wire-or (open-drain) mode enabled 0 = spi signal pins not configured for open-drain. 1 = all four spi signal pins (sck, ss , miso, mosi) configured for open-drain function. this setting is typically used for multi- master and/or multi-sl ave configurations. mmen?spi master mode enable 0 = spi configured in slave mode. 1 = spi configured in master mode. spien?spi enable 0 = spi disabled. 1 = spi enabled. table 64. spi control register (spictl) bits 7 6 5 4 3 2 1 0 field irqe str birq phase clkpol wor mmen spien reset 0 r/w r/w addr f61h
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 135 spi status register the spi status register ( table 65 ) indicates the current state of the spi. all bits revert to their reset state if the spien bit in the spictl register = 0. irq?interrupt request if spien = 1, this bit is set if the str bit in the spictl register is set, or upon completion of an spi master or slave tr ansaction. this bit does not set if spien = 0 and the spi baud rate generator is used as a timer to generate the spi interrupt. 0 = no spi interrupt request pending. 1 = spi interrupt request is pending. ovr?overrun 0 = an overrun error has not occurred. 1 = an overrun error has been detected. col?collision 0 = a multi-master collision (m ode fault) has not occurred. 1 = a multi-master collision (mod e fault) has been detected. abt?slave mode transaction abort this bit is set if the spi is configured in slave mode, a transaction is occurring and ss deasserts before all bits of a character have been transferred as defined by the numbits field of the spimode register. the irq bit al so sets, indicating the transaction has com- pleted. 0 = a slave mode transaction abort has not occurred. 1 = a slave mode transaction abort has been detected. reserved?must be 0. txst?transmit status 0 = no data transmission currently in progress. 1 = data transmission cu rrently in progress. slas?slave select if spi enabled as a slave, table 65. spi status register (spistat) bits 7 6 5 4 3 2 1 0 field irq ovr col abt reserved txst slas reset 01 r/w r/w* r addr f62h note: r/w* = read access. write a 1 to clear the bit to 0.
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 136 0 = ss input pin is asserted (low). 1 = ss input is not asserted (high). if spi enabled as a master, th is bit is not applicable. spi mode register the spi mode register ( table 66 ) configures the character bit width and the direction and value of the ss pin. reserved?must be 0. diag?diagnostic mode control bit this bit is for spi diagnostics. setting this bi t allows the baud rate generator value to be read using the spibrh and spibrl register locations. 0 = reading spibrh, spibrl returns the valu e in the spibrh and spibrl registers 1 = reading spibrh returns bits [15:8] of the spi baud rate generator; and reading spibrl returns bits [7:0] of the spi baud rate counter. the baud rate counter high and low byte values are not buffered. exercise caution if reading the values while the brg is counting. numbits[2:0]?number of data b its per character to transfer this field contains the number of bits to sh ift for each character transfer. for information on valid bit positions when the character length is less than 8-bits, see spi data register description. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits table 66. spi mode register (spimode) bits 7 6 5 4 3 2 1 0 field reserved diag numbits[2:0] ssio ssv reset 0 r/w rr/w addr f63h caution:
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 137 ssio?slave select i/o 0 = ss pin configured as an input. 1 = ss pin configured as an output (master mode only). ssv?slave select value if ssio = 1 and spi configured as a master: 0 = ss pin driven low (0). 1 = ss pin driven high (1). this bit has no effect if ssio = 0 or spi configured as a slave. spi diagnostic state register the spi diagnostic state register ( table 67 ) provides observability of internal state. this is a read only register used for spi diagnostics. scken?shift clock enable 0 = the internal shift clock enable signal is deasserted 1 = the internal shift clock enable signal is asserted (shift register is updates on next system clock) tcken?transmit clock enable 0 = the internal transmit clock enable signal is deasserted. 1 = the internal transmit clock enable signal is asserted. when this is asserted the serial data out is updated on the next system clock (mosi or miso). spistate?spi state machine defines the current state of th e internal spi state machine. table 67. spi diagnostic state register (spidst) bits 7 6 5 4 3 2 1 0 field scken tcken spistate reset 0 r/w r addr f64h
ps019921-0308 serial peripheral interface z8 encore! xp ? f64xx series product specification 138 spi baud rate high and low byte registers the spi baud rate high an d low byte registers ( table 68 and table 69 ) combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. when configured as a general purpose timer, th e spi brg interrupt interval is calculated using the following equation: brh = spi baud rate high byte most significant byte, brg[1 5:8], of the spi baud rate generator?s reload value. brl = spi baud rate low byte least significant byte, brg[7:0], of the spi baud rate generator?s reload value. table 68. spi baud rate high byte register (spibrh) bits 7 6 5 4 3 2 1 0 field brh reset 1 r/w r/w addr f66h table 69. spi baud rate low byte register (spibrl) bits 7 6 5 4 3 2 1 0 field brl reset 1 r/w r/w addr f67h spi brg interrupt interval (s) s ystem clock period (s) brg[15:0] =
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 139 i 2 c controller the i 2 c controller makes the z8 encore! xp ? f64xx series products bus-compatible with the i 2 c protocol. the i 2 c controller consists of two bi directional bus lines?a serial data signal (sda) and a serial cloc k signal (scl). features of the i 2 c controller include: ? transmit and receive operation in master mode ? maximum data rate of 400 kbit/sec ? 7- and 10-bit addressing modes for slaves ? unrestricted number of data bytes transmitted per transfer the i 2 c controller in the z8 encore! xp f64xx series products does not operate in slave mode.
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 140 architecture figure 26 displays the architecture of the i 2 c controller. operation the i 2 c controller operates in master mode to tr ansmit and receive data. only a single master is supported. arbitration between two masters must be accomplished in software. i 2 c supports the follo wing operations: ? master transmits to a 7-bit slave ? master transmits to a 10-bit slave figure 26. i 2 c controller block diagram sda scl i 2 cctl ishift i 2 cdata i 2 cbrh i 2 cbrl shift load tx/rx state machine baud rate generator receive i 2 cstat register bus i 2 c interrupt
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 141 ? master receives from a 7-bit slave ? master receives from a 10-bit slave sda and scl signals i 2 c sends all addresses, data and acknowledge signals over the sda line, most-significant bit first. scl is the common clock for the i 2 c controller. when the sda and scl pin alternate functions are selected for their respective gpio port s, the pins are automatically configured for open -drain operation. the master (i 2 c) is responsible for driving the scl clock signal, although the clock signal can become skewed by a slow slave device. du ring the low period of the clock, the slave pulls the scl signal low to suspend the tran saction. the master releases the clock at the end of the low period and notices that the cloc k remains low instead of returning to a high level. when the slave re leases the clock, the i 2 c controller continues the transaction. all data is transferred in bytes and there is no limit to the amount of da ta transferred in one operation. when transmitting data or acknow ledging read data from the slave, the sda signal changes in the middle of the low period of scl and is sampled in the middle of the high period of scl. i 2 c interrupts the i 2 c controller contains four sources of interrupts?transmit, receive, not acknowledge and baud rate generator. these four interrupt sources are combined into a single interrupt request signal to the interrupt controller. the transmit interrupt is enabled by the ien and txi bits of the control register. the receive and not acknowledge interrupts are enabled by the ien bit of the control register. the baud rate generator interrupt is enabled by the birq and ien bits of the control register. not acknowledge interrupts oc cur when a not acknowledg e condition is received from the slave or sent by the i 2 c controller and neither the start or stop bit is set. the not acknowledge event sets the ncki bit of the i 2 c status register and can only be cleared by setting the start or stop bit in the i 2 c control register. when th is interrupt occurs, the i 2 c controller waits until either the stop or start bit is set before performing any action. in an interrupt servic e routine, the ncki bit should always be checked prior to servicing transmit or receive interrupt cond itions because it indicates the transaction is being terminated. receive interrupts occur when a byte of data has been r eceived by the i 2 c controller (master reading data from slave). this procedure sets the rdrf bit of the i 2 c status register. the rdrf bit is cleared by reading the i 2 c data register. the rdrf bit is set during the acknowledge phase. the i 2 c controller pauses afte r the acknowledge phase until the receive interrupt is cleare d before performing any other action.
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 142 transmit interrupts occur when the tdre bit of the i 2 c status register sets and the txi bit in the i 2 c control register is set. transmit in terrupts occur under the following condi- tions when the transmit data register is empty: ? the i 2 c controller is enabled. ? the first bit of the byte of an address is shifting out and the rd bit of the i 2 c status register is deasserted. ? the first bit of a 10-bit address shifts out. ? the first bit of write data shifts out. writing to the i 2 c data register always clears the trde bit to 0. when tdre is asserted, the i 2 c controller pauses at the beginning of the acknowledge cycle of the byte currently shifting out until the data register is written wi th the next value to send or the stop or start bits are set indicating the curr ent byte is the last one to send. the fourth interrupt source is th e baud rate generator. if the i 2 c controller is disabled (ien bit in the i2cctl register = 0) and the bi rq bit in the i2cctl register = 1, an inter- rupt is generated when the baud rate genera tor counts down to 1. this allows the i 2 c baud rate generator to be used by software as a general purpose timer when ien = 0. software control of i 2 c transactions software can control i 2 c transactions by using the i 2 c controller interrupt, by polling the i 2 c status register or by dma. note that not all products include a dma controller. to use interrupts, the i 2 c interrupt must be enabled in th e interrupt controller. the txi bit in the i 2 c control register must be set to enable transmit interrupts. to control transactions by polling, the interru pt bits (tdre, rdrf and ncki) in the i 2 c status register should be polled. the tdre bit asserts regardless of the state of the txi bit. either or both transmit and receive data movement can be controlled by the dma controller. the dma controlle r channel(s) must be in itialized to select the i 2 c transmit and receive requests. transmit dma reques ts require that the txi bit in the i 2 c control register be set. a transmit (write) dma operation hang s if the slave responds with a not acknowledge before the last byte ha s been sent. after receiving the not acknowledge, the i 2 c controller sets the ncki bit in the status register and pauses until either the stop or start bits in the control register are set. note: caution:
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 143 in order for a receive (read) dma tr ansaction to send a not acknowledge on the last byte, the receive dma must be set up to receive n-1 bytes, then software must set the nak bit and receive the last (nth) byte directly. start and stop conditions the master (i 2 c) drives all start and stop signals an d initiates all transactions. to start a transaction, the i 2 c controller generates a start condition by pu lling the sda signal low while scl is high. to complete a transaction, the i 2 c controller generates a stop condition by creating a low-to-hig h transition of the sda signal while the scl signal is high. the start and stop bits in the i 2 c control register control the sending of the start and stop conditions. a master is also a llowed to end one transaction and begin a new one by issuing a restart. this is accomplished by setting the start bit at the end of a transaction, rather than the stop bit. no te that the start condition not sent until the start bit is set and data has been written to the i 2 c data register. master write and read transactions the following sections provide a recommended procedure for performing i 2 c write and read transactions from the i 2 c controller (master) to slave i 2 c devices. in general software should rely on the tdre, rdrf and nc ki bits of the status register (these bits generate interrupts) to initiate software ac tions. when using interrupts or dma, the txi bit is set to start each transaction and cleare d at the end of each transaction to eliminate a ?trailing? transmit interrupt. caution should be used in using the ack st atus bit within a tr ansaction because it is difficult for software to tell wh en it is updated by hardware. when writing data to a slave, the i 2 c pauses at the beginning of the acknowledge cycle if the data register has not been written with th e next value to be se nt (tdre bit in the i 2 c status register = 1). in this scenario where software is not keeping up with the i 2 c bus (tdre asserted longer than one byte time), th e acknowledge clock cycle for byte n is delayed until the data register is written with byte n + 1, and appears to be grouped with the data clock cycles for byte n+1. if eith er the start or stop bit is set, the i 2 c does not pause prior to the acknowledge cycle because no additional data is sent. when a not acknowledg e condition is received during a write (either during the address or data phases), the i 2 c controller generates the not ac knowledge interrupt (ncki = 1) and pause until either the stop or start b it is set. unless the not acknowledge was received on the last byte, th e data register will already ha ve been written with the next address or data byte to send. in this case th e flush bit of the control register should be set at the same time the stop or start bit is set to remove the stale transmit data and enable subsequent transmit interrupts. when reading data from the slave, the i 2 c pauses after the data acknowledge cycle until the receive interrupt is servic ed and the rdrf bit of the status register is cleared by
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 144 reading the i 2 c data register. once the i 2 c data register has been read, the i 2 c reads the next data byte. address only transacti on with a 7-bit address in the situation where software determines if a slave with a 7-bit address is responding without sending or receiving data, a transactio n can be done which only consists of an address phase. figure 27 displays this ?address only? tr ansaction to determine if a slave with a 7-bit address will acknowledge. as an example, this transaction can be used after a ?write? has been done to a eeprom to dete rmine when the eeprom completes its inter- nal write operation and is once again responding to i 2 c transactions. if the slave does not acknowledge, the transaction can be rep eated until the slave does acknowledge. figure 27. 7-bit address only transaction format follow the steps below for an address only transaction to a 7-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty (tdre = 1) 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. as an alternative this could be a read operation instead of a write operation. 5. software sets the start and stop bits of the i 2 c control register and clears the txi bit. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. software polls the stop bit of the i 2 c control register. hardware deasserts the stop bit when the address only transaction is completed. 9. software checks the ack bit of the i 2 c status register. if the slave acknowledged, the ack bit is = 1. if the slave does not ackn owledge, the ack bit is = 0. the ncki interrupt does not occur in the not acknowl edge case because the stop bit was set. s slave address w = 0 a/a p
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 145 write transaction wi th a 7-bit address figure 28 displays the data transfer format for a 7-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 28. 7-bit addressed slave data transfer format follow the steps below for a transmit operation to a 7-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address has been shifted ou t by the sda signal, the transmit interrupt is asserted (tdre = 1). 9. software responds by writing the transmit data into the i 2 c data register. 10. the i 2 c controller shifts the rest of the ad dress and write bit out by the sda signal. 11. if the i 2 c slave sends an acknowledge (by pulling the sda signal low) during the next high period of scl the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge, the not ac knowledge interrupt occurs (ncki bit is set in the status register, ack bit is cleared). software responds to the not acknowledge interrupt by setting the stop an d flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comple te (ignore the following steps). 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. s slave address w = 0 a data a data a data a/a p/s
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 146 13. the i 2 c controller shifts the data out of usin g the sda signal. after the first bit is sent, the transmit interrupt is asserted. 14. if more bytes remain to be sent, return to step 9 . 15. software responds by setting the stop bit of the i 2 c control register (or start bit to initiate a new transaction). in th e stop case, software clears the txi bit of the i 2 c control register at the same time. 16. the i 2 c controller completes transmission of the data on the sda signal. 17. the slave may either acknowledge or not acknowledge the last byte. because either the stop or start bit is already set , the ncki interrupt does not occur. 18. the i 2 c controller sends the stop (or restart) condition to the i 2 c bus. the stop or start bit is cleared. address only transacti on with a 10-bit address in the situation where software wants to de termine if a slave with a 10-bit address is responding without sending or receiving data, a transaction can be done which only con- sists of an address phase. figure 29 displays this ?address only? transaction to determine if a slave with 10-bit address will acknowledge. as an example, this transaction can be used after a ?write? has been done to a eeprom to determine when the eeprom completes its internal write operation and is once again responding to i 2 c transactions. if the slave does not acknowledge the transaction can be repeat ed until the slave is ab le to acknowledge. figure 29. 10-bit address only transaction format follow the steps below for an address only transaction to a 10-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty (tdre = 1) 4. software responds to the tdre interrupt by writing the fi rst slave address byte. the least-significant bit must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. s slave address 1st 7 bits w = 0 a/a slave address 2nd byte a/a p
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 147 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. if the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comp lete (ignore following steps). 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (2nd byte of address). 13. the i 2 c controller shifts the second address byte out the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by set ting the stop bit in the i 2 c control register. the txi bit can be cleared at the same time. 15. software polls the stop bit of the i 2 c control register. hardware deasserts the stop bit when the transaction is comple ted (stop condition has been sent). 16. software checks the ack bit of the i 2 c status register. if the slave acknowledged, the ack bit is = 1. if the slave does not ackn owledge, the ack bit is = 0. the ncki interrupt do not occur beca use the stop bit was set. write transaction wi th a 10-bit address figure 30 displays the data transfer format for a 10-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 30. 10-bit addressed slave data transfer format s slave address 1st 7 bits w = 0 a slave address 2nd byte a data a data a/a p/s
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 148 the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the read/write control bit (=0). the transmit oper ation is carried out in the same manner as 7- bit addressing. follow the steps below for a transmit op eration on a 10-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts because the i 2 c data register is empty. 4. software responds to the tdre interrupt by writing the firs t slave address byte to the i 2 c data register. the least-significant b it must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. if the i 2 c slave acknowledges the first addres s byte by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comple te (ignore the following steps). 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the second address byte out the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by writing a data byte to the i 2 c data register. 15. the i 2 c controller completes shiftin g the contents of the shift register on the sda signal.
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 149 16. if the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 17 . if the slave does not acknowledge the second ad dress byte or one of the data bytes, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the st op condition on the bus and clears the stop and ncki bits. the tran saction is complete (ignore the following steps). 17. the i 2 c controller shifts the data out by the s da signal. after the first bit is sent, the transmit interrupt is asserted. 18. if more bytes remain to be sent, return to step 14 . 19. if the last byte is currently being sent, software sets the stop bit of the i 2 c control register (or start bit to initiate a new tran saction). in the stop case, software also clears the txi bit of the i 2 c control register at the same time. 20. the i 2 c controller completes transmission of the last data byte on the sda signal. 21. the slave may either acknowledge or not acknowledge the last byte. because either the stop or start bit is already set , the ncki interrupt does not occur. 22. the i 2 c controller sends the stop (or restart) condition to the i 2 c bus and clears the stop (or start) bit. read transaction wi th a 7-bit address figure 31 displays the data transfer format for a read operation to a 7-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data tr ansferred from the slaves to the i 2 c controller. figure 31. receive data transfer format for a 7-bit addressed slave follow the steps below for a read op eration to a 7-bit addressed slave: 1. software writes the i 2 c data register with a 7-bit slave address plus the read bit (=1). 2. software asserts the start bit of the i 2 c control register. 3. if this is a single byte transfer, software asserts the nak bit of the i 2 c control register so that after the first byte of data has been read by the i 2 c controller, a not acknowledge is sent to the i 2 c slave. s slave address r = 1 a data adata a p/s
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 150 4. the i 2 c controller sends the start condition. 5. the i 2 c controller shifts the address a nd read bit out the sda signal. 6. if the i 2 c slave acknowledges the address by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 7 . if the slave does not acknowledge, the not ac knowledge interrupt occurs (ncki bit is set in the status register, ack bit is cleared). software responds to the not acknowledge interrupt by setting the stop bit and clearing the txi bit. the i 2 c controller sends the stop co ndition on the bus and clears the stop and ncki bits. the transaction is complete (ignore the following steps). 7. the i 2 c controller shifts in the byte of data from the i 2 c slave on the sda signal. the i 2 c controller sends a not acknowledge to the i 2 c slave if the nak bit is set (last byte), else it sends an acknowledge. 8. the i 2 c controller asserts the rece ive interrupt (rdrf bit set in the status register). 9. software responds by reading the i 2 c data register which clears the rdrf bit. if there is only one more byte to receive, set the nak bit of the i 2 c control register. 10. if there are more bytes to transfer, return to step 7 . 11. after the last byte is shifted in, a not acknowledge interrupt is generated by the i 2 c controller. 12. software responds by setting the stop bit of the i 2 c control register. 13. a stop condition is sent to the i 2 c slave, the stop and ncki bits are cleared. read transaction wi th a 10-bit address figure 32 displays the read transaction format fo r a 10-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 32. receive data format for a 10-bit addressed slave the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write control bit. s slave address 1st 7 bits w=0 a slave address 2nd byte a s slave address 1st 7 bits r=1 a data adata a p
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 151 follow the steps below for the data transfer for a read operation to a 10-bit addressed slave: 1. software writes 11110b followed by the two address bits and a 0 (write) to the i 2 c data register. 2. software asserts the start and txi bits of the i 2 c control register. 3. the i 2 c controller sends the start condition. 4. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 5. after the first bit has been shifted out, a transmit interrupt is asserted. 6. software responds by writing the lowe r eight bits of address to the i 2 c data register. 7. the i 2 c controller completes shifting of th e two address bits and a 0 (write). 8. if the i 2 c slave acknowledges the first addres s byte by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 9 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comp lete (ignore following steps). 9. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (second address byte). 10. the i 2 c controller shifts out the second address by te. after the first bit is shifted, the i 2 c controller generates a transmit interrupt. 11. software responds by setting the start bit of the i 2 c control register to generate a repeated start and by clearing the txi bit. 12. software responds by writing 11110b followed by the 2-bit slave address and a 1 (read) to the i 2 c data register. 13. if only one byte is to be read , software sets the nak bit of the i 2 c control register. 14. after the i 2 c controller shifts out the 2nd address byte, the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 15 . if the slave does not acknowledge the second address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comple te (ignore the following steps).
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 152 15. the i 2 c controller sends the re peated start condition. 16. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (third address transfer). 17. the i 2 c controller sends 11110b followed by the two most significant bits of the slave read address and a 1 (read). 18. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl if the slave were to not acknowledge at this point (this should not happen because the slave did acknowledge the firs t two address bytes), softwa re would respond by setting the stop and flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is complete (ignore th e following steps). 19. the i 2 c controller shifts in a byte of data from the i 2 c slave on the sda signal. the i 2 c controller sends a not acknowledge to the i 2 c slave if the nak bit is set (last byte), else it sends an acknowledge. 20. the i 2 c controller asserts the rece ive interrupt (rdrf bit set in the status register). 21. software responds by reading the i 2 c data register which clears the rdrf bit. if there is only one more byte to receive, set the nak bit of the i 2 c control register. 22. if there are one or more bytes to transfer, return to step 19 . 23. after the last byte is shifted in, a not acknowledge interrupt is generated by the i 2 c controller. 24. software responds by setting the stop bit of the i 2 c control register. 25. a stop condition is sent to the i 2 c slave and the stop and ncki bits are cleared. i 2 c control register definitions i 2 c data register the i 2 c data register (see table 70 on page 153) holds the data that is to be loaded into the i 2 c shift register during a write to a slave. this register also holds data that is loaded from the i 2 c shift register during a read from a slave. the i 2 c shift register is not acces- sible in the register file address space, but is used only to buffer incoming and outgoing data.
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 153 i 2 c status register the read-only i 2 c status register ( table 71 ) indicates the status of the i 2 c controller. tdre?transmit data register empty when the i 2 c controller is enabled, this bit is 1 when the i 2 c data register is empty. when this bit is set, an in terrupt is generated if the tx i bit is set, except when the i 2 c controller is shifting in data during the rece ption of a byte or when shifting an address and the rd bit is set. this bit is cleared by writing to the i2cdata register. rdrf?receive data register full this bit is set = 1 when the i 2 c controller is en abled and the i 2 c controller has received a byte of data. when asserted, this bit causes the i 2 c controller to generate an interrupt. this bit is cleared by reading the i 2 c data register (unless the read is performed using exe- cution of the on-chip debugger?s read register command). ack?acknowledge this bit indicates the st atus of the acknowledge for the last byte transmitted or received. when set, this bit indicates that an acknowle dge occurred for the last byte transmitted or received. this bit is cleared when ien = 0 or when a not acknowledge occurred for the last byte transmitted or received. it is not reset at the beginning of each transaction and is not reset when this register is read. table 70. i 2 c data register (i2cdata) bits 7 6 5 4 3 2 1 0 field data reset 0 r/w r/w addr f50h table 71. i 2 c status register (i2cstat) bits 7 6 5 4 3 2 1 0 field tdre rdrf ack 10b rd tas dss ncki reset 10 r/w r addr f51h
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 154 software must be cautious in making d ecisions based on this bit within a trans- action because software cannot tell when th e bit is updated by hardware. in the case of write transactions, the i 2 c pauses at the beginning of the acknowledge cycle if the next transmit data or address byte has not been written (tdre = 1) and stop and start = 0. in this case the ack bit is not updated until the transmit interrupt is serviced and the acknowledge cycle for the previous byte completes. for examples of how the ack bit can be used, see address only transaction with a 7-bit address on page 144 and address only transaction with a 10-bit address on page 146. 10b?10-bit address this bit indicates whether a 10- or 7-b it address is being transmitted. after the start bit is set, if the five most-significant bits of the address are 11110b , this bit is set. when set, it is reset once the first byte of the address has been sent. rd?read this bit indicates the direction of transfer of the data. it is active hi gh during a read. the status of this bit is determined by the least-significant bit of the i 2 c shift register after the start bit is set. tas?transmit address state this bit is active high while the ad dress is being shifted out of the i 2 c shift register. dss?data shift state this bit is active high while data is being shifted to or from the i 2 c shift register. ncki?nack interrupt this bit is set high when a not acknowledge condition is rece ived or sent and neither the start nor the stop bit is active. when set, th is bit generates an interrupt that can only be cleared by setting the start or stop bit, allowing you to specify whether to perform a stop or a repeated start . i 2 c control register the i 2 c control register ( table 72 ) enables the i 2 c operation. table 72. i 2 c control register (i2cctl) bits 7 6 5 4 3 2 1 0 field ien start stop birq txi nak flush filten reset 0 r/w r/w r/w1 r/w1 r/w r/w r/w1 w1 r/w addr f52h caution:
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 155 ien?i 2 c enable 1 = the i 2 c transmitter and receiver are enabled. 0 = the i 2 c transmitter and receiver are disabled. start?send start condition this bit sends the start condition. on ce asserted, it is cleared by the i 2 c controller after it sends the start condition or if the ien bit is deasserted. if this bit is 1, it cannot be cleared to 0 by writing to the register. after this bit is set, the start condition is sent if there is data in the i 2 c data or i 2 c shift register. if there is no da ta in one of these registers, the i 2 c controller waits until the data register is written. if this bit is set while the i 2 c controller is shifting out data , it generates a start condition af ter the byte shifts and the acknowledge phase completes. if the stop bit is also set, it also waits until the stop condition is sent before the sending the start condition. stop?send stop condition this bit causes the i 2 c controller to issue a stop co ndition after the byte in the i 2 c shift register has completed transm ission or after a byte has been received in a receive operation. once set, this bit is reset by the i 2 c controller after a stop condition has been sent or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the register. birq?baud rate genera tor interrupt request this bit allows the i 2 c controller to be used as an additional timer when the i 2 c controller is disabled. this bit is ignored when the i 2 c controller is enabled. 1 = an interrupt occurs every time the baud rate generator counts down to one. 0 = no baud rate generator interrupt occurs. txi?enable tdre interrupts this bit enables the tran smit interrupt when the i 2 c data register is empty (tdre = 1). 1 = transmit interrupt (and dm a transmit request) is enabled. 0 = transmit interrupt (and dma transmit request) is disabled. nak?send nak this bit sends a not acknowledge condition after the next byte of data has been read from the i 2 c slave. once asserted, it is deasserted after a not acknowledge is sent or the ien bit is deasserted. if this bit is 1, it cannot be cleared to 0 by writing to the register. flush?flush data setting this bit to 1 clears the i 2 c data register and sets the tdre bit to 1. this bit allows flushing of the i 2 c data register when a not acknowle dge interrupt is received after the data has been sent to the i 2 c data register. reading this bit always returns 0. filten?i 2 c signal filter enable this bit enables low-pass dig ital filters on the sda and scl input signals. these filters reject any input pulse with periods less than a full system clock cycle. the filters introduce a 3-system clock cycle latency on the inputs. 1 = low-pass filters are enabled. 0 = low-pass filters are disabled.
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 156 i 2 c baud rate high and low byte registers the i 2 c baud rate high and low byte register s (tables 73 and 73) combine to form a 16-bit reload value, brg[15:0], for the i 2 c baud rate generator. when the i 2 c is disabled, the baud rate generato r can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the i 2 c by clearing the ien bit in the i 2 c control register to 0. 2. load the desired 16-bit count value into the i 2 c baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the i 2 c control register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: brh = i 2 c baud rate high byte most significant byte , brg[15:8], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrh register returns the current value of the i 2 c baud rate counter[15:8]. table 73. i 2 c baud rate high byte register (i2cbrh) bits 7 6 5 4 3 2 1 0 field brh reset ffh r/w r/w addr f53h interrupt interval (s) sys tem clock period (s) brg 15:0 [] = note:
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 157 brl = i 2 c baud rate low byte least significant byte, brg[7:0], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrl register returns the current value of the i 2 c baud rate counter[7:0]. i 2 c diagnostic state register the i 2 c diagnostic state register ( table 75 ) provides observability of internal state. this is a read only register used for i 2 c diagnostics and manufacturing test. sclin?value of serial clock input signal sdain?value of the serial data input signal stpcnt?value of the internal stop count control signal txrxstate?value of the internal i 2 c state machine table 74. i 2 c baud rate low byte register (i2cbrl) bits 7 6 5 4 3 2 1 0 field brl reset ffh r/w r/w addr f54h table 75. i 2 c diagnostic state register (i2cdst) bits 7 6 5 4 3 2 1 0 field sclin sdain stpcnt txrxstate reset x0 r/w r addr f55h note:
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 158 txrxstate state description 0_0000 idle state 0_0001 start state 0_0010 send/receive data bit 7 0_0011 send/receive data bit 6 0_0100 send/receive data bit 5 0_0101 send/receive data bit 4 0_0110 send/receive data bit 3 0_0111 send/receive data bit 2 0_1000 send/receive data bit 1 0_1001 send/receive data bit 0 0_1010 data acknowledge state 0_1011 second half of data acknowledge state used only for not acknowledge 0_1100 first part of stop state 0_1101 second part of stop state 0_1110 10-bit addressing: acknowledge state for 2nd address byte 7-bit addressing: address acknowledge state 0_1111 10-bit address: bit 0 (least significant bit) of 2nd address byte 7-bit address: bit 0 (least significant bit) (r/w) of address byte 1_0000 10-bit addressing: bit 7 (most significant bit) of 1st address byte 1_0001 10-bit addressing: bit 6 of 1st address byte 1_0010 10-bit addressing: bit 5 of 1st address byte 1_0011 10-bit addressing: bit 4 of 1st address byte 1_0100 10-bit addressing: bit 3 of 1st address byte 1_0101 10-bit addressing: bit 2 of 1st address byte 1_0110 10-bit addressing: bit 1 of 1st address byte 1_0111 10-bit addressing: bit 0 (r/w) of 1st address byte 1_1000 10-bit addressing: acknowledge state for 1st address byte 1_1001 10-bit addressing: bit 7 of 2nd address byte 7-bit addressing: bit 7 of address byte 1_1010 10-bit addressing: bit 6 of 2nd address byte 7-bit addressing: bit 6 of address byte 1_1011 10-bit addressing: bit 5 of 2nd address byte 7-bit addressing: bit 5 of address byte 1_1100 10-bit addressing: bit 4 of 2nd address byte 7-bit addressing: bit 4 of address byte
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 159 i 2 c diagnostic c ontrol register the i 2 c diagnostic register ( table 76 ) provides control over diagnostic modes. this regis- ter is a read/write register used for i 2 c diagnostics. diag = diagnostic control bit - selects read back value of the baud rate reload regis- ters. 0 = normal mode. reading the baud rate high and low byte re gisters returns the baud rate reload value. 1 = diagnostic mode. reading the baud rate high and low byte registers returns the baud rate counter value. 1_1101 10-bit addressing: bit 3 of 2nd address byte 7-bit addressing: bit 3 of address byte 1_1110 10-bit addressing: bit 2 of 2nd address byte 7-bit addressing: bit 2 of address byte 1_1111 10-bit addressing: bit 1 of 2nd address byte 7-bit addressing: bit 1 of address byte table 76. i 2 c diagnostic control register (i2cdiag) bits 7 6 5 4 3 2 1 0 field reserved diag reset 0 r/w rr/w addr f56h txrxstate state description
ps019921-0308 i2c controller z8 encore! xp ? f64xx series product specification 160
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 161 direct memory access controller the z8 encore! xp ? f64xx series direct memory access (dma) controller provides three independent direct memory access ch annels. two of the channels (dma0 and dma1) transfer data between the on-chip pe ripherals and the register file. the third channel (dma_adc) controls the adc oper ation and transfers single-shot mode adc output data to the register file. operation dma0 and dma1 operation dma0 and dma1, referred to collectively as dma x , transfer data either from the on-chip peripheral control registers to the register f ile, or from the register file to the on-chip peripheral control regi sters. the sequence of operations in a dma x data transfer is: 1. dma x trigger source requests a dma data transfer. 2. dma x requests control of the system bus (address and data) from the ez8 cpu. 3. after the ez8 cpu acknowled ges the bus request, dma x transfers either a single byte or a two-byte word (depending upon conf iguration) and then returns system bus control back to the ez8 cpu. 4. if current address equals end address: ?dma x reloads the original start address ? if configured to generate an interrupt, dma x sends an interrupt request to the interrupt controller ? if configured for single-pass operation, dma x resets the den bit in the dma x control register to 0 and the dma is disabled. if current address does not equal end addr ess, the current address increments by 1 (single-byte transfer) or 2 (two-byte word transfer). configuring dma0 and dma1 for data transfer follow the steps below to config ure and enable dma0 or dma1: 1. write to the dma x i/o address register to set the re gister file address identifying the on-chip peripheral control register. the uppe r nibble of the 12-bit address for on-chip peripheral control registers is always fh . the full address is {fh, dma x _io[7:0]}. 2. determine the 12-bit start and end register file addresses. the 12-bit start address is given by {dma x _h[3:0], dma_start[7:0]}. the 12-bit end address is given by {dma x _h[7:4], dma_end[7:0]}.
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 162 3. write the start and end register f ile address high nibbles to the dma x end/start address high nibble register. 4. write the lower byte of the start address to the dma x start/current address register. 5. write the lower byte of the end address to the dma x end address register. 6. write to the dma x control register to complete the following: ? select loop or single-pass mode operation ? select the data transfer direction (eithe r from the register file ram to the on- chip peripheral control register; or from the on-chip peripheral control register to the register file ram) ? enable the dma x interrupt request, if desired ? select word or byte mode ? select the dma x request trigger ? enable the dma x channel dma_adc operation dma_adc transfers data from the adc to the register file. the sequence of operations in a dma_adc data transfer is: 1. adc completes conversion on the current adc input channel and signals the dma controller that two-bytes of ad c data are ready for transfer. 2. dma_adc requests control of the system bus (address and data) from the ez8 cpu. 3. after the ez8 cpu acknowledges the bus request, dma_adc transfers the two-byte adc output value to the register file and th en returns system bus control back to the ez8 cpu. 4. if the current adc analog input is the highest numbered input to be converted: ? dma_adc resets the adc analog input nu mber to 0 and initiates data conversion on adc analog input 0. ? if configured to generate an interrupt, dma_adc sends an interrupt request to the interrupt controller if the current adc analog input is not the highest numbered input to be converted, dma_adc initiates data conversion in the next higher numbered adc analog input. configuring dma_adc for data transfer follow the steps below to co nfigure and enable dma_adc: 1. write the dma_adc address register with th e 7 most-significant bits of the register file address for data transfers. 2. write to the dma_adc control regi ster to complete the following:
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 163 ? enable the dma_adc interrupt request, if desired ? select the number of adc analog inputs to convert ? enable the dma_adc channel when using the dma_adc to perform conversions on multiple adc inputs, the analog-to-digital converter must be configured for single-shot mode. if the adc_in field in the dma_adc control re gister is greater than 000b, the adc must be in single-shot mode. continuous mode operation of the adc can only be used in conjunction with dma_adc if the adc_in field in the dma_adc control register is re- set to 000b to enable conversi on on adc anal og input 0 only. dma control register definitions dma x control register the dma x control register (see table 77 on page 163) enables and selects the mode of operation for dma x . den?dma x enable 0 = dma x is disabled and data transfer requests are disregarded. 1 = dma x is enabled and initiates a data transfer upon receipt of a request from the trigger source. dle?dma x loop enable 0 = dma x reloads the original start address and is then disabled after the end address data is transferred. table 77. dma x control register (dma x ctl) bits 7 6 5 4 3 2 1 0 field den dle ddir irqen wsel rss reset 0 r/w r/w addr fb0h, fb8h caution:
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 164 1 = dma x , after the end address data is tran sferred, reloads the original start address and continues operating. ddir?dma x data transfer direction 0 = register file on-chip peripheral control register. 1 = on-chip peripheral control register register file. irqen?dma x interrupt enable 0 = dma x does not generate any interrupts. 1 = dma x generates an interrupt when the end address data is transferred. wsel?word select 0 = dma x transfers a single byte per request. 1 = dma x transfers a two-byte word per re quest. the address for the on-chip peripheral control register must be an even address. rss?request trigger source select the request trigger source select field determ ines the peripheral that can initiate a dma transfer. the corresponding interrupts do not ne ed to be enabled within the interrupt con- troller to initiate a dma transfer. however, if the request trigger so urce can enable or disable the interrupt request sent to the interru pt controller, the interrupt request must be enabled within the request trigger source block. 000 = timer 0. 001 = timer 1. 010 = timer 2. 011 = timer 3. 100 = dma0 control register: uart0 received data register contains valid data. dma1 control register: uart0 transmit data register empty. 101 = dma0 control register: uart1 received data register contains valid data. dma1 control register: uart1 transmit data register empty. 110 = dma0 control register: i 2 c receiver interrupt. dm a1 control register: i 2 c transmitter interrupt register empty. 111 = reserved. dma x i/o address register the dma x i/o address register ( table 78 ) contains the low byte of the on-chip peripheral address for data transfer. the full 12-bit register file address is given by {fh,
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 165 dma x _io[7:0]}. when the dma is configured for two-byte word transfers, the dma x i/o address register must cont ain an even numbered address. dma_io?dma on-chip peripheral control register address this byte sets the low byte of the on-chip peripheral control register address on register file page fh (addresses f00h to fffh ). dma x address high nibble register the dma x address high register ( table 79 ) specifies the upper four bits of address for the start/current and end addresses of dma x . dma_end_h?dma x end address high nibble these bits, used with the dma x end address low register, fo rm a 12-bit end address. the full 12-bit address is given by {dma_end_h[3:0], dma_end[7:0]}. dma_start_h?dma x start/current address high nibble these bits, used with the dma x start/current address low register, form a 12-bit start/current address. the full 12-bit addr ess is given by {dma_start_h[3:0], dma_start[7:0]}. table 78. dma x i/o address register (dma x io) bits 7 6 5 4 3 2 1 0 field dma_io reset x r/w r/w addr fb1h, fb9h table 79. dma x address high nibble register (dma x h) bits 7 6 5 4 3 2 1 0 field dma_end_h dma_start_h reset x r/w r/w addr fb2h, fbah
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 166 dma x start/current address low byte register the dma x start/current address low register, in conjunction with the dma x address high nibble register, forms a 12-bit start/curre nt address. writes to this register set the start address for dma operations. each time the dma completes a data transfer, the 12-bit start/current address increments by eith er 1 (single-byte transfer) or 2 (two-byte word transfer). reads from this register retu rn the low byte of the current address to be used for the next dma data transfer. dma_start?dma x start/current address low these bits, with the four lower bits of the dma x _h register, form the 12-bit start/current address. the full 12-bit address is given by {dma_start_h[3:0], dma_start[7:0]}. dma x end address low byte register the dma x end address low byte register ( table 80 ), in conjunction with the dma x _h register ( table 81 ), forms a 12-bit end address. dma_end?dma x end address low these bits, with the four upper bits of the dma x _h register, form a 12-bit address. this address is the ending location of the dma x transfer. the full 12-bit address is given by {dma_end_h[3:0], dma_end[7:0]}. table 80. dma x start/current address low byte register (dma x start) bits 7 6 5 4 3 2 1 0 field dma_start reset x r/w r/w addr fb3h, fbbh table 81. dma x end address low byte register (dma x end) bits 7 6 5 4 3 2 1 0 field dma_end reset x r/w r/w addr fb4h, fbch
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 167 dma_adc address register the dma_adc address register ( table 83 ) points to a block of the register file to store adc conversion values as displayed in table 82 . this register contains the seven most- significant bits of the 12-bit register file ad dresses. the five least-significant bits are cal- culated from the adc analog in put number (5-bit base address is equal to twice the adc analog input number). the 10 -bit adc conversion data is st ored as two bytes with the most significant byte of the adc data stored at the even numbered register file address. table 82 provides an example of the register file addresses if the dma_adc address register contains the value 72h. table 82. dma_adc register file address example adc analog input register file address (hex) 1 0 720h-721h 1 722h-723h 2 724h-725h 3 726h-727h 4 728h-729h 572ah-72bh 6 72ch-72dh 7 72eh-72fh 8 730h-731h 9 732h-733h 10 734h-735h 11 736h-737h 1 dmaa_addr set to 72h. table 83. dma_adc address register (dmaa_addr) bits 7 6 5 4 3 2 1 0 field dmaa_addr reserved reset x r/w r/w addr fbdh
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 168 dmaa_addr?dma_adc address these bits specify the seven mo st-significant bits of the 12-bit register file addresses used for storing the adc output data. the adc analog input number defines the five least-significant bits of the register file address. full 12-bit address is {dmaa_addr[7:1], 4-bit adc analog input number, 0}. reserved this bit is reserved and must be 0. dma_adc control register the dma_adc control register ( table 84 on page 168) enables and sets options (dma enable and interrupt en able) for adc operation. daen?dma_adc enable 0 = dma_adc is disabled and the adc analog input number (adc_in) is reset to 0. 1 = dma_adc is enabled. irqen?interrupt enable 0 = dma_adc does not generate any interrupts. 1 = dma_adc generates an interrupt after transferring data from the last adc analog input specified by the adc_in field. reserved these bits are reserved and must be 0. adc_in?adc analog input number these bits set the number of adc analog inpu ts to be used in th e continuous update (data conversion followed by dma data transf er). the conversion always begins with adc analog input 0 and then progresses seq uentially through the other selected adc analog inputs. 0000 = adc analog input 0 updated. 0001 = adc analog inputs 0-1 updated. 0010 = adc analog inputs 0-2 updated. 0011 = adc analog inputs 0-3 updated. 0100 = adc analog inputs 0-4 updated. table 84. dma_adc control register (dmaactl) bits 7 6 5 4 3 2 1 0 field daen irqen reserved adc_in reset 0 r/w r/w addr fbeh
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 169 0101 = adc analog inputs 0-5 updated. 0110 = adc analog inputs 0-6 updated. 0111 = adc analog inputs 0-7 updated. 1000 = adc analog inputs 0-8 updated. 1001 = adc analog inputs 0-9 updated. 1010 = adc analog inputs 0-10 updated. 1011 = adc analog inputs 0-11 updated. 1100-1111 = reserved. dma status register the dma status register ( table 85 on page 169) indicates the dma channel that gener- ated the interrupt and the ad c analog input that is currently undergoing conversion. reads from this register reset the interrupt request indicator bits ( irqa , irq1 , and irq0 ) to 0. therefore, software in terrupt service routines that read this register must pro- cess all three interrupt sources from the dma. cadc[3:0]?current adc analog input this field identifies the analog input that the adc is currently converting. reserved this bit is reserved and must be 0. irqa?dma_adc interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. 0 = dma_adc is not the source of th e interrupt from the dma controller. 1 = dma_adc completed transfer of data fro m the last adc analog input and generated an interrupt. irq1?dma1 interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. 0 = dma1 is not the source of the interrupt from the dma controller. 1 = dma1 completed transfer of data to/from the end address and generated an interrupt. irq0?dma0 interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. table 85. dma_adc status register (dmaa_stat) bits 7 6 5 4 3 2 1 0 field cadc[3:0] reserved irqa irq1 irq0 reset 0 r/w r addr fbfh
ps019921-0308 direct memory access controller z8 encore! xp ? f64xx series product specification 170 0 = dma0 is not the source of the interrupt from the dma controller. 1 = dma0 completed transfer of data to/from the end address and generated an interrupt.
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 171 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to a 10-bit binary number. the features of the sigma-delta adc include: ? 12 analog input sources are multiple xed with general-purpose i/o ports ? interrupt upon conversion complete ? internal voltage re ference generator ? direct memory access (dma) controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs architecture figure 33 displays the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the adc. the ad c converts an analog input signal to its digital representation. the 12-input analog multiplexer selects one of the 12 analog input sources. the adc requires an input referenc e voltage for the conversion. the voltage reference for the conversion may be input through the external vref pin or generated internally by the voltage reference generator.
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 172 figure 33. analog-to-digital converter block diagram the sigma-delta adc architecture provides al ias and image attenuation below the ampli- tude resolution of the adc in the frequency range of dc to one-half the adc clock rate (one-fourth the system clock rate). the ad c provides alias free conversion for frequen- cies up to one-half the adc clock rate. thus the sigma-delta adc exhibits high noise immunity making it ideal for em bedded applications. in add ition, monotonicity (no miss- ing codes) is guaranteed by design. operation automatic power-down if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powere d-down. from this power-down state, the adc requires 40 system clock cycles to po wer-up. the adc powers up when a conver- sion is requested using the adc control register. analog-to-digital converter ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 ana8 ana9 ana10 ana11 analog input multiplexer anain[3:0] internal voltage reference generator vref analog input reference input
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 173 single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. follow the steps below for setting up the adc and initiating a single- shot conversion: 1. enable the desired analog inputs by configuring the general-purpose i/o pins for alternate function. this configuration disa bles the digital input and output drivers. 2. write to the adc control register to co nfigure the adc and begin the conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select one of th e 12 analog input sources. ?clear cont to 0 to select a single-shot conversion. ? write to the vref bit to enable or disable the in ternal voltage reference generator. ?set cen to 1 to start the conversion. 3. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. when the conversion is complete, the adc control logic performs the following operations: ? 10-bit data result written to {adcd_h[7:0], adcd_l[7:6]}. ? cen resets to 0 to indicate the conversion is complete. ? an interrupt request is sent to the interrupt controller. 5. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data register s. an interrupt is generated after each con- version. in continuous mode, you must be aware that adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its dig- ital filter. step changes at the input are not seen at the next output from the adc. the response of the adc (in all mo des) is limited by the input signal bandwidth and the latency. caution:
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 174 follow the steps below for setting up the adc and initiating con tinuous conversion: 1. enable the desired analog input by configuring the general-purpose i/o pins for alternate function. this disables th e digital input and output driver. 2. write to the adc control register to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to the anain[3:0] field to select one of th e 12 analog input sources. ?set cont to 1 to select continuous conversion. ? write to the vref bit to enable or disable the in ternal voltage reference generator. ?set cen to 1 to start the conversions. 3. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 4. thereafter, the adc writes a new 10-bit data result to {adcd_h[7:0], adcd_l[7:6]} every 256 system clock cycles. an interrupt request is sent to the interrupt controller when e ach conversion is complete. 5. to disable continuous conversion, clear the cont bit in the adc control register to 0. dma control of the adc the direct memory access (d ma) controller can control ope ration of the adc includ- ing analog input selection and conversion en able. for more information on the dma and configuring for adc operations, see direct memory access controller on page 161.
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 175 adc control register definitions adc control register the adc control register selects the analog input channel and initiates the analog-to-dig- ital conversion. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears this bit to 0 when a conversion has been completed. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. reserved?must be 0. vref 0 = internal voltage referen ce generator enabled. the vref pin should be left uncon- nected (or capacitively coupled to analog gr ound) if the internal voltage reference is selected as the adc reference voltage. 1 = internal voltage re ference generator disabled. an exte rnal voltage reference must be provided through the vref pin. cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles. anain?analog input select these bits select the analog input for conver sion. for information on the port pins avail- able with each package style, see signal and pin descriptions on page 7. do not enable unavailable analog inputs. 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 table 86. adc control register (adcctl) bits 7 6 5 4 3 2 1 0 field cen reserved vref cont anain[3:0] reset 01 0 r/w r/w addr f70h
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 176 0101 = ana5 0110 = ana6 0111 = ana7 1000 = ana8 1001 = ana9 1010 = ana10 1011 = ana11 11xx = reserved. adc data high byte register the adc data high byte register ( table 87 ) contains the upper eight bits of the 10-bit adc output. during a single-shot conversion, this value is invalid. access to the adc data high byte register is read-only. the full 10-bit adc result is given by {adcd_h[7:0], adcd_l[7:6]}. reading the adc data high byte register latches data in the adc low bits register. adcd_h?adc data high byte this byte contains the upper eight bits of the 10-bit adc output. these bits are not valid during a single-shot conversion. during a con tinuous conversion, the last conversion out- put is held in this register. the se bits are undefined after a reset. adc data low bits register the adc data low bits register ( table 88 ) contains the lower two bits of the conversion value. the data in the adc data low bits register is latched each time the adc data high byte register is read. reading this register always returns the lower two bits of the conversion last read into the adc high byte register. access to the adc data low bits register is read-only. the full 10-b it adc result is given by {adcd_h[7:0], adcd_l[7:6]}. table 87. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcd_h reset x r/w r addr f72h
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 177 adcd_l?adc data low bits these are the least significant two bits of th e 10-bit adc output. these bits are undefined after a reset. reserved these bits are reserved and are always undefined. table 88. adc data low bits register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcd_l reserved reset x r/w r addr f73h
ps019921-0308 analog-to-digital converter z8 encore! xp ? f64xx series product specification 178
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 179 flash memory the products in the z8 encore! xp ? f64xx series feature up to 64 kb (65,536 bytes) of non-volatile flash memory with read/write/e rase capability. the flash memory can be programmed and erased in-circuit by either user code or through the on-chip debugger. the flash memory array is arranged in 512 byte per page. the 512 byte page is the minimum flash block size that can be erased . the flash memory is also divided into 8 sectors which can be protected from programmi ng and erase operations on a per sector basis. table 89 describes the flash memory configuration for each device in the z8 encore! xp f64xx series. table 90 on page 180 lists the sector address ranges. figure 34 on page 180 displays the flash memory arrangement. table 89. flash memory configurations part number flash size number of pages flash memory addresses sector size number of sectors pages per sector z8f162x 16k (16,384) 32 0000h - 3fffh 2k (2048) 8 4 z8f242x 24k (24,576) 48 0000h - 5fffh 4k (4096) 6 8 z8f322x 32k (32,768) 64 0000h - 7fffh 4k (4096) 8 8 z8f482x 48k (49,152) 96 0000h - bfffh 8k (8192) 6 16 z8f642x 64k (65,536) 128 0000h - ffffh 8k (8192) 8 16
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 180 figure 34. flash memory arrangement table 90. flash memory sector addresses sector number flash sector address ranges z8f162x z8f242x z8f322x z8f482x z8f642x 0 0000h-07ffh 0000h-0fffh 0000h-0fffh 0000h-1fffh 0000h-1fffh 1 0800h-0fffh 1000h-1fffh 1000h-1fffh 2000h-3fffh 2000h-3fffh 2 1000h-17ffh 2000h-2fffh 2000h-2fffh 4000h-5fffh 4000h-5fffh 3 1800h-1fffh 3000h-3fffh 3000h-3fffh 6000h-7fffh 6000h-7fffh 4 2000h-27ffh 4000h-4fffh 4000h-4fffh 8000h-9fffh 8000h-9fffh 5 2800h-2fffh 5000h-5fffh 5000h-5fffh a000h-bfffh a000h-bfffh 6 3000h-37ffh n/a 6000h-6fffh n/a c000h-dfffh 7 3800h-3fffh n/a 7000h-7fffh n/a e000h-ffffh 64 kb flash program memory 0000h 128 pages 512 bytes per page 01ffh 0200h 03ffh fc00h fdffh fe00h ffffh 0400h 05ffh fa00h fbffh addresses
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 181 information area table 91 describes the z8 encore! xp ? f64xx series informatio n area. this 512 byte information area is accessed by se tting bit 7 of the page select register to 1. when access is enabled, the information ar ea is mapped into flash memory and overlays the 512 bytes at addresses fe00h to ffffh . when the information area a ccess is enabled, ldc instruc- tions return data from the information area. cpu instruction fetches always comes from flash memory regardless of the information area access bit. access to the information area is read-only. operation the flash controller provides the proper sign als and timing for byte programming, page erase, and mass erase of the flash memory. the flash controller contains a protection mechanism, via the flash control register (f ctl), to prevent accid ental programming or erasure. the following subsections provide details on the various operations (lock, unlock, sector protect, byte programm ing, page erase, and mass erase). table 91. z8 encore! xp f64xx series information area map flash memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros fe54h-ffffh reserved
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 182 timing using the flash frequency registers before performing a program or erase operat ion on the flash memory, you must first configure the flash frequency high and lo w byte registers. the flash frequency registers allow programming and erasure of the flash with system clock frequencies ranging from 20 khz through 20 mhz (the va lid range is limited to the device operating frequencies). the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit flash frequency value must contain the system clock frequency in khz. this value is calculated using the following equation:. flash programming and erasure are not supported for system clock frequencies below 20 khz, above 20 mhz, or outs ide of the device operating frequency range. the flash frequency high and low byte registers must be loaded with the correct value to insure proper flash programming and erase operations. flash read protection the user code contained within the flash me mory can be protected from external access. programming the flash read protect option bit prevents reading of user code by the on- chip debugger or by using the flash contro ller bypass mode. for mo re information, see option bits on page 191 and on-chip debugger on page 195. flash write/erase protection the z8 encore! xp ? f64xx series provides several levels of protection against acciden- tal program and erasure of the flash memory co ntents. this protection is provided by the flash controller unlock mechanism, the flash sector protect register, and the flash write protect option bit. flash controller unlock mechanism at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory , the flash controller must be unlocked. after unlocking the flash controller, the flash can be programmed or erased. any value written by user code to the flash control regist er or page select register out of sequence will lock the flash controller. follow the steps below to unlock th e flash controller from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be programmed or erased to the page select register. ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------ = caution:
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 183 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the pa ge written in step 2 to the page select register. flash sector protection the flash sector protect register can be configured to prevent sectors from being programmed or erased. once a sector is prot ected, it cannot be unprotected by user code. the flash sector protect register is cleared after reset and any previously written protection values is lost. user code must write this register in their initialization routine if they want to enable sector protection. the flash sector protect register shares its register file address with the page select register. the flash sector protect register is accessed by writing the flash control register with 5eh . once the flash sector protect register is selected, it can be accessed at the page select register address. when user code writes the flash sector protect register, bits can only be set to 1. thus, sectors can be prot ected, but not unprotected, via register write operations. writing a value other than 5eh to the flash control register de-selects the flash sector protect register and re-enables access to the page select register. follow the steps below to setup the flash sector protect register from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to sel ect the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. flash write protection option bit the flash write protect option bit can be en abled to block all program and erase opera- tions from user code. for more information, see option bits on page 191. byte programming when the flash controller is unlocked, writes to flash memory from user code will pro- gram a byte into the flash if the address is located in the unlocked page. an erased flash byte contains all ones ( ffh ). the programming operation can only be used to change bits from one to zero. to change a flash bit (or mu ltiple bits) from zero to one requires a page erase or mass erase operation. byte programming can be accomplished using the ez8 cpu?s ldc or ldci instructions. for a description of the ldc and ldci instructions, refer to ez8 ? cpu core user man- ual (um0128) .
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 184 while the flash controller programs the flas h memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to op erate. interrupts that occur when a program- ming operation is in progress are serviced once the programming op eration is complete. to exit programming mode and lo ck the flash controller, write 00h to the flash control register. user code cannot program flash memory on a page that lies in a protected sector. when user code writes memory locations, only addr esses located in the unlocked page are pro- grammed. memory writes outside of the unlocked page are ignored. each memory location must not be pr ogrammed more than twice before an erase occurs. follow the steps below to program the flash from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write the page of memory to be pr ogrammed to the page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the page written in step 2 to the page select register. 6. write flash memory using ldc or ldci instructions to program the flash. 7. repeat step 6 to program additional memory locations on th e same page. 8. write 00h to the flash control register to lock the flash controller. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the page select register identifies the page to be erased. while the flash controller executes the page erase operation, the ez8 cpu idles but the system clock and on-chip pe ripherals continue to operate. the ez8 cpu resumes operation after the page erase opera tion completes. interrupts that occur when the page erase operation is in progress are ser viced once the page erase operation is com- plete. when the page erase operation is co mplete, the flash controller returns to its locked state. only pages located in unprotected sectors can be erased. follow the steps below to perform a page erase operation: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be erased to the page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. caution:
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 185 5. re-write the page written in step 2 to the page select register. 6. write the page erase command 95h to the flash control register. mass erase the flash memory cannot be mass erased by user code. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster programming algorithms by controlling the flash programming signals directly. flash controller bypass is recommended for gang programming applications and large volume customers who do not require in-c ircuit programming of the flash memory. for more information on bypassing the flash controller, refer to third-party flash pro- gramming support for z8 encore! available for download at www.zilog.com . flash controller beh avior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored. ? the flash sector protect register is ig nored for programming and erase operations. ? programming operations are not limited to the page selected in the page select register. ? bits in the flash sector protect regi ster can be written to one or zero. ? the second write of the page select regist er to unlock the flash controller is not necessary. ? the page select register can be written when the flash controller is unlocked. ? the mass erase command is enabled th rough the flash control register. for security reasons, flash controller allows only a single page to be opened for write/erase. when writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page. caution:
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 186 flash control register definitions flash control register the flash control register ( table 92 ) unlocks the flash contro ller for programming and erase operations, or to select th e flash sector protect register. the write-only flash control register shares its register file address with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command. 63h = mass erase command 5eh = flash sector protect register select. * all other commands, or any command out of sequence, lock the flash controller. flash status register the flash status register ( table 93 ) indicates the current state of the flash controller. this register can be read at any time. the read-o nly flash status register shares its register file address with the write-o nly flash control register. table 92. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 0 r/w w addr ff8h table 93. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 0 r/w r addr ff8h
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 187 reserved these bits are reserved and must be 0. fstat?flash controller status 00_0000 = flash controller locked 00_0001 = first unlock command received 00_0010 = second unlock command received 00_0011 = flash controller unlocked 00_0100 = flash sector protect register selected 00_1xxx = program operation in progress 01_0xxx = page erase operation in progress 10_0xxx = mass erase operation in progress page select register the page select (fps) register ( table 94 ) selects one of the 128 available flash memory pages to be erased or programmed. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory locations with the 7 most significant bits of the address given by the page field are erased to ffh . the page select register shares its register file address with the flash sector protect reg- ister. the page select register cannot be acc essed when the flash sector protect register is enabled. info_en?informat ion area enable 0 = information area is not selected. 1 = information area is selected. the inform ation area is mapped into the flash memory address space at addresses fe00h through ffffh . page?page select this 7-bit field selects the flash memory page for programming and page erase opera- tions. flash memory address[15:9] = page[6:0]. table 94. page select register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 0 r/w r/w addr ff9h
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 188 flash sector protect register the flash sector protect register ( table 95 ) protects flash memory sectors from being programmed or erased from user code. the flas h sector protect register shares its regis- ter file address with the page select register. the flash sector protect register can be accessed only after writing the flash control register with 5eh . user code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). sect n ?sector protect 0 = sector n can be programmed or erased from user code. 1 = sector n is protected and cannot be prog rammed or erased from user code. * user code can only write bits from 0 to 1. flash frequency high a nd low byte registers the flash frequency high and low byte registers ( table 96 and table 97 ) combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit flash frequency registers must be written with the system clock frequency in khz for program and erase operations. calcul ate the flash frequency value using the fol- lowing equation: flash programming and erasure is not su pported for system clock frequencies be- low 20 khz, above 20 mhz, or outside of the valid operating frequency range for the device. the flash frequency high and low byte registers must be loaded with the correct value to insure proper program and erase times. table 95. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sect7 sect6 sect5 sect4 sect3 sect2 sect1 sect0 reset 0 r/w r/w1 addr ff9h note: r/w1 = register is accessible for read operations. r egister can be written to 1 only (via user code). ffreq[15:0] ffreqh[7:0],ffreql[7:0] {} system clock frequency 1000 ----------------------------------------------------------- - == caution:
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 189 ffreqh and ffreql?flash frequency high and low bytes these 2 bytes, {ffreqh[7:0], ffreql[7:0]}, contain the 16-bit flash frequency value. table 96. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 0 r/w r/w addr ffah table 97. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w addr ffbh
ps019921-0308 flash memory z8 encore! xp ? f64xx series product specification 190
ps019921-0308 option bits z8 encore! xp ? f64xx series product specification 191 option bits option bits allow user configuration of certain aspects of the z8 encore! xp ? f64xx series operation. the feature configuration data is stored in the flash memory and read during reset. the features available for control via the option bits are: ? watchdog timer time-out response selection?interrupt or reset. ? watchdog timer enabled at reset. ? the ability to prevent unwa nted read access to user code in flash memory. ? the ability to prevent accident al programming and erasure of the user code in flash memory. ? voltage brownout configuration-always enabled or disabled during stop mode to reduce stop mode power consumption. ? oscillator mode selection-for high, medium, and low power crystal oscillators, or external rc oscillator. operation option bit configuration by reset each time the option bits are programmed or erased, the device must be reset for the change to take place. duri ng any reset operation (system reset, reset, or stop mode recovery), the option bits ar e automatically read from the flash memory and written to option configuration registers. the option co nfiguration registers control operation of the devices within the z8 en core! xp f64xx series. optio n bit control is established before the device exits reset and the ez8 cp u begins code execution. the option config- uration registers are not part of the register file and are not accessible for read or write access. option bit address space the first two bytes of flash memory at addresses 0000h (see table 98 on page 192) and 0001h (see table 99 on page 193) are reserved for the u ser option bits. the byte at flash memory address 0000h configures user options. the byte at flash memory address 0001h is reserved for future use an d must remain unprogrammed.
ps019921-0308 option bits z8 encore! xp ? f64xx series product specification 192 flash memory address 0000h wdt_res?watchdog timer reset 0 = watchdog timer time-out generates an interrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watchdog timer time-out causes a short r eset. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watchdog timer always on 0 = watchdog timer is automa tically enabled upon applicat ion of system power. watch- dog timer can not be disabled except during stop mode (if configured to power down during stop mode). 1 = watchdog timer is enabled upon execution of the wdt instruction. once enabled, the watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the default for unprogrammed (erased) flash. osc_sel[1:0]?oscillator mode selection 00 = on-chip oscillator configured for use with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium fre quency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). 11 = maximum power for use with high frequen cy crystals (8.0 mhz to 20.0 mhz). this setting is the default for un programmed (erased) flash. vbo_ao?voltage brownout protection always on 0 = voltage brownout protection is disabl ed in stop mode to reduce total power consumption. 1 = voltage brownout protection is always enabled including during stop mode. this setting is the defa ult for unprogrammed (erased) flash. rp?read protect 0 = user program code is inaccessible. lim ited control features are available through table 98. flash option bits at flash memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_re s wdt_ao osc_sel[1:0] vbo_ao rp reserved fwp reset u r/w r/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps019921-0308 option bits z8 encore! xp ? f64xx series product specification 193 the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. reserved these option bits are reserved for future use and must always be 1.this setting is the default for unprogram med (erased) flash. fwp?flash write protect (flash version only) flash memory address 0001h reserved these option bits are reserved for future use and must always be 1. this setting is the default for unprogram med (erased) flash. fwp description 0 programming, page erase, and mass erase through user code is disabled. mass erase is available through the on-chip debugger. 1 programming, and page erase are enabled for all of flash program memory. table 99. options bits at flash memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved reset u r/w r/w addr program memory 0001h note: u = unchanged by reset. r = read-only. r/w = read/write.
ps019921-0308 option bits z8 encore! xp ? f64xx series product specification 194
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 195 on-chip debugger the z8 encore! xp ? f64xx series products contain an integrated on-chip debugger (ocd) that provides advanced debugging features including: ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints ? execution of ez8 cpu instructions architecture the on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, and debug controller. figure 35 displays the architecture of the on-chip debugger. figure 35. on-chip debugger block diagram operation ocd interface the on-chip debugger uses the dbg pin for communication with an external host. this one-pin interface is a bi-directional open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. auto-baud detector/generator transmitter receiver debug controller system clock dbg pin ez8 tm cpu control
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 196 the serial data on the dbg pin is sent us ing the standard asynchronous data format defined in rs-232. this pin can interface the z8 encore! xp ? f64xx series products to the serial port of a host pc using minimal external hardware.two different methods for connecting the dbg pin to an rs-2 32 interface are depicted in figure 36 and figure 37 on page 196. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must always be connected to v dd through an external pull-up resist or to ensure proper operation. figure 36. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) figure 37. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) caution: rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10 k ? diode rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10 k ? open-drain buffer
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 197 debug mode the operating characteristics of the z8 encore! xp ? f64xx series devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez 8 cpu, unless directed by the ocd to execute specific instructions. ? the system clock operates unless in stop mode. ? all enabled on-chip peripherals operate unless in stop mode. ? automatically exits halt mode. ? constantly refreshes the wa tchdog timer, if enabled. entering debug mode the device enters debug mode following any of the following operations: ? writing the dbgmode bit in the ocd control register to 1 using the ocd interface. ? ez8 cpu execution of a brk (breakpoint) instruction (when enabled). ? if the dbg pin is low when the device exits reset, the on-chip debugger automatically puts the device into debug mode. exiting debug mode the device exits debug mode following any of the following operations: ? clearing the dbgmode bit in the ocd control register to 0. ? power-on reset ? voltage brownout reset ? asserting the reset pin low to initiate a reset. ? driving the dbg pin low while the device is in stop mode initiates a system reset. ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (l east-significant bit first), and 1 stop bit (see figure 38 ). figure 38. ocd data format startd0d1d2d3d4d5d6d7stop
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 198 ocd auto-baud detector/generator to run over a range of baud rates (bits per second) with various system clock frequencies, the on-chip debugger has an auto-baud dete ctor/generator. after a reset, the ocd is idle until it receives data. the ocd requires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits). the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. the theoretical maxi- mum baud rate is the system clock frequency divided by 4. this theoretical maximum is possible for low noise desi gns with clean signals. table 100 lists minimum and recom- mended maximum baud rates fo r sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. the auto-baud dete ctor/generator can then be reconfigured by sending 80h . ocd serial errors the on-chip debugger can detect any of th e following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low). ? framing error (received stop bit is low). ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd). when the ocd detects one of these errors, it aborts any command currently in progress, transmits a serial break 4096 system clock cy cles long back to th e host, and resets the auto-baud detector/generator. a framing er ror or transmit collision may be caused by the host sending a serial break to the ocd. because of the open-drain nature of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. table 100. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbits/s) minimum baud rate (kbits/s) 20.0 2500 39.1 1.0 125.0 1.96 0.032768 (32 khz) 4.096 0.064
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 199 the host transmits a serial break on the dbg pin when first connecting to the z8 encore! xp ? f64xx series devices or when recovering from an error. a serial break from the host resets the auto-baud generator/detector but does not reset the ocd control register. a serial break leaves the device in debug mo de if that is the cu rrent mode. the ocd is held in reset until the end of the serial brea k when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd idles the ez8 cpu and en ters debug mode. if breakpoints are not enabled, the ocd ignores the brk signal an d the brk instruction operates as an nop. if breakpoints are enabled, the ocd can be configured to automa tically enter debug mode, or to loop on the break instruction. if the ocd is configured to loop on the brk instruction, then th e cpu is still enabled to servic e dma and interrupt requests. the loop on brk instruction can be used to service interrupts in the background. for interrupts to be serviced in the background, there cannot be any breakpoints in the inter- rupt service routine. otherwise, the cpu stops on the breakpoint in the interrupt routine. for interrupts to be serviced in the background, interrupts mu st also be enabled. debug- ging software should not auto matically enable interrupts when using this feature, since interrupts are typically disabled during criti cal sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data). software can poll the idle bit of the ocdstat register to determine if the ocd is loop- ing on a brk instruction. when software want s to stop the cpu on the brk instruction it is looping on, software shou ld not set the dbgmode bit of the ocdctl register. the cpu may have vectored to and be in the middle of an interrupt service routine when this bit gets set. instead, software must clear th e brklp bit. this action allows the cpu to finish the interrupt service routine it may be in and return the brk instruction. when the cpu returns to the brk instruction it was prev iously looping on, it automatically sets the dbgmode bit and enter debug mode. software detects that the majority of th e ocd commands are still disabled when the ez8 tm cpu is looping on a brk instruction. the ez8 cpu must be stopped and the part must be in debug mode before these commands can be issued. breakpoints in flash memory the brk instruc tion is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the desired address, over- writing the current instruction. to remove a breakpoint, the correspon ding page of flash memory must be erased and reprogrammed with the original data.
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 200 on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands beco me available unless the user code and control registers are protected by progr amming the read protect option bit ( rp ). the read protect option bit prevents the code in memory from being read out of the z8 encore! xp ? f64xx series products. when this option is enab led, several of the ocd commands are disabled. table 101 contains a summary of the on-chip debugger com- mands. each ocd command is described in detail in the bu lleted list following table 101 . table 101 indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by programming the read pro- tect option bit. table 101. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit read ocd revision 00h yes - read ocd status register 02h yes - read runtime counter 03h - - write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes - write program counter 06h - disabled read program counter 07h - disabled write register 08h - only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h - disabled write program memory 0ah - disabled read program memory 0bh - disabled write data memory 0ch - disabled read data memory 0dh - disabled
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 201 in the following list of ocd commands, data and commands sent from the host to the on- chip debugger are identified by ? dbg command/data ?. data sent from the on-chip debugger back to the host is identified by ? dbg data ? ? read ocd revision (00h) ?the read ocd revision command determines the version of the on-chip debugger. if ocd commands are added, removed, or changed, this revisi on number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? read ocd status register (02h) ?the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl register. when the read protect option bit is enabled, the dbgmode bit (ocdctl[7]) can only be set to 1, it cannot be cleared to 0 and the only method of puttin g the device back into normal operating mode is to reset the device. dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s progr am counter (pc). if the device is not in read program memory crc 0eh - - reserved 0fh - - step instruction 10h - disabled stuff instruction 11h - disabled execute instruction 12h - disabled reserved 13h - ffh - - table 101. on-chip debugger commands (continued) debug command command byte enabled when not in debug mode? disabled by read protect option bit
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 202 debug mode or if the read protect option bit is enabled, the program counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] ? read program counter (07h) ?the read program counter command reads the value in the ez8 cpu?s program counter (p c). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). if the device is not in debug mode , the address and data values are discarded. if the read protect option bit is enabled, then only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? read register (09h) ?the read register command reads data from the register file. data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equiva lent to the ldc and ldci instructions. data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). the on-chip flash controller mu st be written to and unlocked for the programming operation to occur. if the flas h controller is not unlocked, the data is discarded. if the device is not in debug mo de or if the read protect option bit is enabled, the data is discarded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 203 ? read program memory (0bh) ?the read program memo ry command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? write data memory (0ch) ?the write data memory co mmand writes data to data memory. this command is equivalent to th e lde and ldei instructions. data can be written 1-65536 bytes at a tim e (65536 bytes can be written by setting size to zero). if the device is not in debug mo de or if the read protect option bit is enabled, the data is discarded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory command reads from data memory. this command is equivalent to th e lde and ldei instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc command computes and returns the crc (cyclic redu ndancy check) of program memory using the 16-bit crc-ccitt polynomial. if the de vice is not in debug mode, this command returns ffffh for the crc value. unlike most other ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the result. the delay is a function of the progra m memory size and is approximately equal to the system clock period multiplied by th e number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0]
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 204 ? step instruction (10h) ?the step instruction co mmand steps one assembly instruction at the current program counte r (pc) location. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the fi rst byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the in struction has been overwritten by a breakpoint. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an entire instruction to be executed to the ez 8 cpu. this command can also step over breakpoints. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the re ad protect option bit is enabled, the ocd ignores this command dbg 12h dbg 1-5 byte opcode
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 205 on-chip debugger control register definitions ocd control register the ocd control register ( table 102 ) controls the state of the on-chip debugger. this register enters or exits debug mode and enables the brk instruction. a ?reset and stop? function can be achieved by writing 81h to this register. a ?reset and go? function can be achieved by writing 41h to this register. if the device is in debug mode, a ?run? function can be implemented by writing 40h to this register. dbgmode?debug mode setting this bit to 1 causes the device to en ter debug mode. when in debug mode, the ez8 cpu stops fetching new instructions. clea ring this bit causes the ez8 cpu to start running again. this bit is au tomatically set when a brk inst ruction is decoded and break- points are enabled. if the read protect option bit is enabled, this bit can only be cleared by resetting the device, it cannot be written to 0. 0 = thez8 encore! xp ? f64xx series device is operating in normal mode. 1 = the z8 encore! xp ? f64xx series device is in debug mode. brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h). by default, break- points are disabled and the brk instruction beha ves like a nop. if this bit is set to 1 and a brk instruction is decoded, the ocd take s action dependent upon the brkloop bit. 0 = brk instruction is disabled. 1 = brk instruction is enabled. dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, then the ocd sends an debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. brkloop?breakpoint loop this bit determines what ac tion the ocd takes when a brk instruction is decoded if breakpoints are enabled (brken is 1). if this bit is 0, then the dbgmode bit is automat- ically set to 1 and the ocd entered debug mode. if brkloop is set to 1, then the ez8 cpu loops on the brk instruction. table 102. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack brkloop reserved rst reset 0 r/w r/w r r/w
ps019921-0308 on-chip debugger z8 encore! xp ? f64xx series product specification 206 0 = brk instruction sets dbgmode to 1. 1 = ez8 cpu loops on brk instruction. reserved these bits are reserved and must be 0. rst?reset setting this bit to 1 resets the z8 encore! xp ? f64xx series devices. the devices go through a normal power-on reset sequence w ith the exception that the on-chip debug- ger is not reset. this bit is automatica lly cleared to 0 when the reset finishes. 0 = no effect 1 = reset the z8 encore! xp ? f64xx series device ocd status register the ocd status register ( table 103 ) reports status information about the current state of the debugger and the system. idle?cpu idling this bit is set if the part is in debug mo de (dbgmode is 1), or if a brk instruction occurred since the last time oc dctl was written. this can be used to determine if the cpu is running or if it is idling. 0 = the ez8 cpu is running. 1 = the ez8 cpu is either stopped or looping on a brk instruction. halt?halt mode 0 = the device is not in halt mode. 1 = the device is in halt mode. rpen?read protect option bit enabled 0 = the read protect option bit is disabled (1). 1 = the read protect option bit is enab led (0), disabling many ocd commands. reserved these bits are always 0. table 103. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field idle halt rpen reserved reset 0 r/w r
ps019921-0308 on-chip oscillator z8 encore! xp ? f64xx series product specification 207 on-chip oscillator the products in the z8 encore! xp ? f64xx series feature an on-chip oscillator for use with external crystals with fre quencies from 32 khz to 20 mhz. in addition, the oscillator can support external rc networks with osc illation frequencies up to 4 mhz or ceramic resonators with oscillation frequencies up to 20 mhz. this oscillator generates the pri- mary system clock fo r the internal ez8 ? cpu and the majority of the on-chip peripherals. alternatively, the x in input pin can also accept a cmos-l evel clock input signal (32 khz? 20 mhz). if an external cloc k generator is used, the x out pin must be left unconnected. when configured for use with cr ystal oscillators or external cl ock drivers, the frequency of the signal on the x in input pin determines the frequency of the system clock (that is, no internal clock divider). in rc operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. operating modes the z8 encore! xp f64xx series products support four different oscillator modes: ? on-chip oscillator configured for use with external rc networks (<4 mhz). ? minimum power for use with very low fre quency crystals (32 khz to 1.0 mhz). ? medium power for use with medium frequ ency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). ? maximum power for use with high frequency crystals or ceramic resonators (8.0 mhz to 20.0 mhz). the oscillator mode is selected through u ser-programmable option bits. for more infor- mation, see option bits on page 191. crystal oscillator operation figure 39 on page 208 displays a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20 mhz. recommended 20 mhz crystal specifications are provided in table 104 on page 208. resistor r1 is optional and limits total power dissipation by th e crystal. the printed circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscilla- tion does not occur, reduce the values of capacitors c1 and c2 to decrease loading.
ps019921-0308 on-chip oscillator z8 encore! xp ? f64xx series product specification 208 figure 39. recommended 20 mhz crystal oscillator configuration table 104. recommended crystal oscillat or specifications (20 mhz operation) parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )25 ? maximum load capacitance (c l ) 20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22 pf c1 = 22 pf crystal xout xin on-chip oscillator r1 = 220 ?
ps019921-0308 on-chip oscillator z8 encore! xp ? f64xx series product specification 209 oscillator operation with an external rc network the external rc oscillator mode is app licable to timing insen sitive applications. figure 40 displays a recommended configuration fo r connection with an external resistor- capacitor (rc) network. figure 40. connecting the on-chip oscillator to an external rc network an external resistance value of 45 k ? is recommended for oscillator operation with an external rc network. the minimum resistan ce value to ensure operation is 40 k ?. the typical oscillator frequency can be esti mated from the values of the resistor ( r in k ? ) and capacitor ( c in pf) elements usi ng the following equation: figure 41 displays the typical (3.3 v and 25 c) oscillator frequ ency as a function of the capacitor ( c in pf) employed in the rc network assuming a 45 k ? external resistor. for very small values of c, the pa rasitic capacitance of the osc illator xin pin and the printed circuit board should be included in th e estimation of the oscillator frequency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sensitivity to external parasitics, external capacitance values in excess of 20 pf are recommended. c x in r v dd oscillator frequency (khz) 1 6 10 0.4 rc () 4 c () + -------------------------------------------------------- - =
ps019921-0308 on-chip oscillator z8 encore! xp ? f64xx series product specification 210 figure 41. typical rc oscillator frequency as a function of the external capacitance with a 45 k ? resistor when using the external rc oscillator mode, the oscillator may stop oscillat- ing if the power supply drops below 2.7 v, but before the power supply drops to the voltage brown-out threshold. the osci llator will resume oscillation as soon as the supply voltage exceeds 2.7 v. 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 211 electrical characteristics absolute maximum ratings stresses greater than those listed in table 105 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, unused inputs must be tied to one of the supply voltages (v dd or v ss ). table 105. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +125 c storage temperature -65 +150 c voltage on any pin with respect to v ss -0.3 +5.5 v 1 voltage on v dd pin with respect to v ss -0.3 +3.6 v maximum current on input and/or inactive output pin -5 +5 a maximum output current from active output pin -25 +25 ma 80-pin qfp maximum ratings at ?40 c to 70 c total power dissipation 550 mw maximum current into v dd or out of v ss 150 ma 80-pin qfp maximum ratings at 70 c to 125 c total power dissipation 200 mw maximum current into v dd or out of v ss 56 ma 68-pin plcc maximum ratings at ?40 c to 70 c total power dissipation 1000 mw maximum current into v dd or out of v ss 275 ma 68-pin plcc maximum ratings at 7 0 c to 125 c total power dissipation 500 mw maximum current into v dd or out of v ss 140 ma 64-pin lqfp maximum ratings at ?40 c to 70 c total power dissipation 1000 mw
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 212 maximum current into v dd or out of v ss 275 ma 64-pin lqfp maximum ratings at 70 c to 125 c total power dissipation 540 mw maximum current into v dd or out of v ss 150 ma 44-pin plcc maximum ratings at ?40 c to 70 c total power dissipation 750 mw maximum current into v dd or out of v ss 200 ma 44-pin plcc maximum rati ngs at 70 c to 125 c total power dissipation 295 mw maximum current into v dd or out of v ss 83 ma 44-pin lqfp maximum ratings at ?40 c to 70 c total power dissipation 750 mw maximum current into v dd or out of v ss 200 ma 44-pin lqfp maximum ratings at 70 c to 125 c total power dissipation 360 mw maximum current into v dd or out of v ss 100 ma note: this voltage applies to all pins except the following: v dd, avdd, pins supporting analog input (ports b and h), reset , and where noted otherwise. table 105. absolute maximum ratings (continued) parameter minimum maximum units notes
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 213 dc characteristics table 106 lists the dc characteristics of the z8 encore! xp ? f64xx series products. all voltages are referenced to v ss , the primary system ground. table 106. dc characteristics symbol parameter t a = ?40 c to 125 c units conditions minimum typical maximum v dd supply voltage 3.0 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v for all input pins except reset , dbg, xin v il2 low level input voltage -0.3 ? 0.2*v dd v for reset , dbg, and xin. v ih1 high level input voltage 0.7*v dd ? 5.5 v port a, c, d, e, f, and g pins. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v port b and h pins. v ih3 high level input voltage 0.8*v dd ?v dd +0.3 v reset , dbg, and xin pins v ol1 low level output voltage standard drive ??0.4vi ol = 2 ma; vdd = 3.0 v high output drive disabled. v oh1 high level output voltage standard drive 2.4 ? ? v i oh = -2 ma; vdd = 3.0 v high output drive disabled. v ol2 low level output voltage high drive ??0.6vi ol = 20 ma; vdd = 3.3 v high output drive enabled t a = -40 c to +70 c v oh2 high level output voltage high drive 2.4 ? ? v i oh = -20 ma; vdd = 3.3 v high output drive enabled; t a = -40 c to +70 c v ol3 low level output voltage high drive ??0.6vi ol = 15 ma; vdd = 3.3 v high output drive enabled; t a = +70 c to +105 c v oh3 high level output voltage high drive 2.4 ? ? v i oh = 15 ma; vdd = 3.3 v high output drive enabled; t a = +70 c to +105 c v ram ram data retention 0.7 ? ? v i il input leakage current -5 ? +5 av dd = 3.6 v; v in = vdd or vss 1 i tl tri-state leakage current -5 ? +5 av dd = 3.6 v
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 214 c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capacitance ? 8.0 2 ?pf c xout xout pad capacitance ? 9.5 2 ?pf i pu weak pull-up current 30 100 350 ma v dd = 3.0 - 3.6 v i dda active mode supply current (see figure 42 on page 216 and figure 43 on page 217) gpio pins configured as outputs ?1116 12 ma v dd = 3.6 v, fsysclk = 20 mhz v dd = 3.3 v ?911 9 ma v dd = 3.6 v, fsysclk = 10 mhz v dd = 3.3 v i ddh halt mode supply current (see figure 44 on page 218 and figure 45 on page 219) gpio pins configured as outputs 47 5 ma v dd = 3.6 v, fsysclk = 20 mhz v dd = 3.3 v ?3 5 4 ma v dd = 3.6 v, fsysclk = 10 mhz v dd = 3.3 v table 106. dc characteristics (continued) symbol parameter t a = ?40 c to 125 c units conditions minimum typical maximum
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 215 i dds stop mode supply current (see figure 46 and figure 47 ) gpio pins configured as outputs ? 520 700 650 a v dd = 3.6 v, vbo and wdt enabled v dd = 3.3 v ?1025 20 a v dd = 3.6 v, t a = 0 to 70 oc vbo disabled wdt enabled v dd = 3.3 v ?80 70 a v dd = 3.6 v, t a = ?40 to +105 oc vbo disabled wdt enabled v dd = 3.3 v ?250 150 a v dd = 3.6 v, t a = ?40 to +125 oc vbo disabled wdt enabled v dd = 3.3 v 1 this condition excludes all pins that have on-chip pull-ups, when driven low. 2 these values are provided for design guidan ce only and are not tested in production. table 106. dc characteristics (continued) symbol parameter t a = ?40 c to 125 c units conditions minimum typical maximum
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 216 figure 42 displays the typical active mode current consumption while operating at 25 oc versus the system clock frequency. all gpio pins are configured as outputs and driven high. stics figure 42. typical active mode idd versus system clock frequency 0 3 6 9 12 15 05101520 system clock frequency (mhz) idd (ma ) 3.0v 3.3v 3.6v
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 217 figure 43 displays the maximum active mode curre nt consumption across the full operat- ing temperature range of the device and versus the system clock frequency. all gpio pins are configured as outputs and driven high. stics figure 43. maximum active mode idd versus system clock frequency 0 3 6 9 12 15 0 5 10 15 20 system clock frequency (mhz) idd (ma) 3.0v 3.3v 3.6v
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 218 figure 44 displays the typical current consump tion in halt mode wh ile operating at 25 oc versus the system clock frequency. a ll gpio pins are configured as outputs and driven high. figure 44. typical halt mode idd versus system clock frequency 0 1 2 3 4 5 0 5 10 15 20 system clock frequency (mhz) halt idd (ma ) 3.0v 3.3v 3.6v
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 219 figure 44 displays the maximum halt mode curre nt consumption across the full operat- ing temperature range of the device and versus the system clock frequency. all gpio pins are configured as outputs and driven high. figure 45. maximum halt mode icc versus system clock frequency 0 1 2 3 4 5 6 0 5 10 15 20 system clock frequency (mhz) halt idd (ma) 3.0v 3.3v 3.6v
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 220 figure 46 displays the maximum current consump tion in stop mode with the vbo and watchdog timer enabled versus the power supp ly voltage. all gpio pins are configured as outputs and driven high. figure 46. maximum stop mode idd with vbo enabled versus power supply voltage 400 450 500 550 600 650 700 3.0 3.2 3.4 3.6 vdd (v) stop idd (microamperes) -40/105c 0/70c 25c typical
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 221 figure 47 displays the maximum current consump tion in stop mode with the vbo dis- abled and watchdog timer enabled versus th e power supply voltage. all gpio pins are configured as outputs and driven high. disabling the watchdog timer and its internal rc oscillator in stop mode will provide some additional reduction in stop mode current consumption. this small current reduction would be indistinquishable on the scale of figure 47 . figure 47. maximum stop mode idd with vbo disabled versus power supply voltage 0.00 20.00 40.00 60.00 80.00 100.00 120.00 3.0 3.2 3.4 3.6 vdd (v) stop idd (microamperes) 25c typical 0/70c -40/105c -40/+125c
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 222 on-chip peripheral ac and dc electrical characteristics table 107. power-on reset and voltage brownout electrical characteristics and timing symbol parameter t a = ?40 c to 125 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.40 2.70 2.90 v v dd = v por v vbo voltage brownout reset voltage threshold 2.30 2.60 2.85 v v dd = v vbo v por to v vbo hysteresis 50 100 ? mv starting v dd voltage to ensure valid power-on reset. ?v ss ?v t ana power-on reset analog delay ?50? sv dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay ? 6.6 ? ms 66 wdt oscillator cycles (10 khz) + 16 system clock cycles (20 mhz) t vbo voltage brownout pulse rejection period ?10? sv dd < v vbo to generate a reset. t ramp time for vdd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms 1 data in the typical column is from characterization at 3.3 v and 0 c. these values are provided for design guidance only and are not tested in production.
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 223 table 108. external rc oscillator electrical characteristics and timing symbol parameter t a = ?40 c to 125 c units conditions minimum typical 1 maximum v dd operating voltage range 2.70 1 ??v r ext external resistance from xin to vdd 40 45 200 k ? v dd = v vbo c ext external capacitance from xin to vss 0201000pf f osc external rc oscillation frequency ?? 4mhz 1 when using the external rc oscillator mode, the oscillat or may stop oscillating if the power supply drops below 2.7 v, but before the power supply drops to the voltage brow n-out threshold. the oscillator will resume oscillation as soon as the supply voltage exceeds 2.7 v. table 109. reset and stop mode recovery pin timing symbol parameter t a = ?40 c to 125 c units conditions minimum typical maximum t reset reset pin assertion to initiate a system reset. 4? ?t clk not in stop mode. t clk = system clock period. t smr stop mode recovery pin pulse rejection period 10 20 40 ns reset , dbg, and gpio pins configured as smr sources.
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 224 table 110 list the flash memory electrical characteristics and timing. table 111 lists the watchdog timer electrical characteristics and timing. table 112 provides electrical characteristics an d timing information for the analog-to- digital converter. figure 48 displays the input frequ ency response of the adc. table 110. flash memory electrical characteristics and timing parameter v dd = 3.0?3.6 v t a = ?40 c to 125 c units notes minimum typical maximum flash byte read time 50 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ??2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 c endurance, ?40 c to 105 c 10,000 ? ? cycles program/erase cycles endurance, 106 c to 125 c 1,000 ? ? cycles program/erase cycles table 111. watchdog timer electrical characteristics and timing symbol parameter v dd = 3.0?3.6 v t a = ?40 c to 125 c units conditions minimum typical maximum f wdt wdt oscillator frequency 5 10 20 khz i wdt wdt oscillator current including internal rc oscillator ?< 1 5 a
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 225 table 112. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 v?3.6 v t a = ?40 c to 125 c units conditions minimum typical maximum resolution 10 ? ? bits external v ref = 3.0 v; differential nonlinearity (dnl) -1.0 +1.0 lsb guaranteed by design integral nonlinearity (inl) -3.0 + 1.0 3.0 lsb external v ref = 3.0 v dc offset error -35 ? 25 mv dc offset error -50 ? 25 mv 44-pin lqfp, 44-pin plcc, and 68-pin plcc packages. v ref internal reference voltage 1.9 2.0 2.4 v v dd = 3.0 v - 3.6 v t a = -40 c to 105 c vc ref voltage coefficient of internal reference voltage ?78 ?mv/vv ref variation as a function of avdd. tc ref temperature coefficient of internal reference voltage ?1 ?mv/c single-shot conversion period ? 5129 ? cycles system clock cycles continuous conversion period ? 256 ? cycles system clock cycles r s analog source impedance ? ? 150 ? recommended zin input impedance 150 k ? v ref external reference voltage avdd v avdd <= vdd. when using an external reference voltage, decoupling capacitance should be placed from vref to avss. i ref current draw into vref pin when driving with external source. 25.0 40.0 a
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 226 figure 48. analog-to-digital converter frequency response frequency (khz) 0.9 0.8 0.7 0.6 0.3 0.4 0.2 0.1 0 frequency response 1 0.5 0 5 10 15 20 25 30 -6 db -3 db adc magnitude transfer function (linear scale)
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 227 ac characteristics the section provides information on the ac characteristics and tim ing. all ac timing information assumes a standard load of 50 pf on all outputs. table 113 lists the z8 encore! xp ? f64xx series ac characteristics and timing. table 113. ac characteristics symbol parameter v dd = 3.0 v?3.6v t a = ?40 c to 125 c units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash memory. 0.032768 20.0 mhz program or erasure of the flash memory. f xtal crystal oscillator freq uency 0.032768 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver. t xin crystal oscillator clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 ns t xinl system clock low time 20 ns t xinr system clock rise time ? 3 ns t clk = 50 ns. slower rise times can be tolerated with longer clock periods. t xinf system clock fall time ? 3 ns t clk = 50 ns. slower fall times can be tolerated with longer clock periods.
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 228 general-purpose i/o port input data sample timing figure 49 displays timing of the gpio port input sampling. table 114 lists the gpio port input timing. figure 49. port input sample timing table 114. gpio port input timing parameter abbreviation delay (ns) min max t s_port port input transition to xin fall setup time (not pictured) 5? t h_port xin fall to port input transition hold time (not pictured) 6? t smr gpio port pin pulse widt h to insure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk gpio pin port value changes to 0 0 latched into port input input value gpio input data latch clock data register gpio data read on data bus gpio data register value 0 read by ez8 cpu
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 229 general-purpose i/o port output timing figure 50 and table 115 provide timing informa tion for gpio port pins. figure 50. gpio port output timing table 115. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 20 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 230 on-chip debugger timing figure 51 and table 116 provide timing information for the dbg pin. the dbg pin tim- ing specifications assume a 4 s maximum rise and fall time. figure 51. on-chip debugger timing table 116. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 30 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 10 ? t 4 dbg to xin rise input hold time 5 ? dbg frequency system clock/4 xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 231 spi master mode timing figure 52 and table 117 provide timing information for spi master mode pins. timing is shown with sck rising edge used to source mosi output data, sck falling edge used to sample miso input data. timing on the ss output pin(s) is controlled by software. figure 52. spi master mode timing table 117. spi master mode timing parameter abbreviation delay (ns) min max spi master t 1 sck rise to mosi output valid delay -5 +5 t 2 miso input to sck (receive edge) setup time 20 t 3 miso input to sck (receive edge) hold time 0 sck mosi t1 (output) miso t2 t3 (input) output data input data
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 232 spi slave mode timing figure 53 and table 118 provide timing information for the spi slave mode pins. timing is shown with sck rising edge used to sour ce miso output data, sck falling edge used to sample mosi input data. figure 53. spi slave mode timing table 118. spi slave mode timing parameter abbreviation delay (ns) minimum maximum spi slave t 1 sck (transmit edge) to miso output valid delay 2 * xin period 3 * xin period + 20 nsec t 2 mosi input to sck (receive edge) setup time 0 t 3 mosi input to sck (receive edge) hold time 3 * xin period t 4 ss input assertion to sck setup 1 * xin period sck miso t1 (output) mosi t2 t3 (input) output data input data ss (input) t4
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 233 i 2 c timing figure 54 and table 119 provide timing information for i 2 c pins. figure 54. i 2 c timing table 119. i 2 c timing parameter abbreviation delay (ns) minimum maximum i 2 c t 1 scl fall to sda output delay scl period/4 t 2 sda input to scl rising edge setup time 0 t 3 sda input to scl fallin g edge hold time 0 scl sda t1 (output) sda t2 (input) output data input data (output) t3
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 234 uart timing figure 55 and table 120 provide timing information for uart pins for the case where the clear to send input pin (cts ) is used for flow control. in this example, it is assumed that the driver enable polarity has been configured to be active low and is represented here by de . the cts to de assertion delay (t1) assumes the uart transmit data register has been loaded with data prior to cts assertion. figure 55. uart timing with cts table 120. uart timing with cts parameter abbreviation delay (ns) minimum maximum t 1 cts fall to de assertion delay 2 * xin period 2 * xin period + 1 bit period t 2 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 3 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 t 2 txd (output) de (output) cts (input) start bit 0 t 3 bit 7 parity stop bit 1 end of stop bit(s)
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 235 figure 56 and table 121 provide timing information for uart pins for the case where the clear to send input signal (cts ) is not used for flow contro l. in this example, it is assumed that the driver enable polarity ha s been configured to be active low and is represented here by de . de asserts after the uart transmit data register has been written. de remains asserted for multiple characters as long as the transmit data register is written with the next character befo re the current character has completed. figure 56. uart timing without cts table 121. uart timing without cts parameter abbreviation delay (ns) minimum maximum t 1 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 2 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 txd (output) de (output) start bit 0 t 2 bit 7 parity stop bit 1 end of stop bit(s)
ps019921-0308 electrical characteristics z8 encore! xp ? f64xx series product specification 236
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 237 ez8 ? cpu instruction set assembly language pro gramming introduction the ez8 cpu assembly language provides a me ans for writing an application program without having to be concerned with actua l memory addresses or machine instruction formats. a program written in assembly langua ge is called a source program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to re present the instructio ns themselves. the opcodes identify the in struction while the operands represe nt memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called statements. each statement can contain la bels, operations, oper ands and comments. labels can be assigned to a particular inst ruction step in a source program. the label identifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine language program called the obje ct code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h .
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 238 assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination?, but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed if you prefer manual program coding or intend to implement your own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0?255 or, using escaped mode addressing, a working register r0 - r15. if the contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: refer to the device-specific product specificatio n to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and address modes are re presented by a notationa l shorthand that is described in table 122 . assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 239 . table 123 contains additional symbols that are used throughout the instruction summary and instruction set description sections. table 122. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? refer to condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. repr esents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a number in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to -128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represents a number in the range of 00h to ffh x indexed #index the register or regist er pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 240 assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. condition codes the c, z, s and v flags control the operati on of the conditional jump (jp cc and jr cc) instructions. sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which form s bits 7:4 of the conditional jump instruc- tions. the condition codes are summarized in table 124 . some binary condition codes can be created using more than one assembly code mnemonic. the result of the flag test oper- ation decides if the cond itional jump is executed. table 123. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix table 124. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false ? 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 241 ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true ? 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 1011 b ugt unsigned greater than (c = 0 and z = 0) = 1 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0 table 124. condition codes (continued) binary hex assembly mnemonic definition flag test operation
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 242 table 125 through table 132 contain the instructions belo nging to each group and the number of operands required for each instruction. some instru ctions appear in more than one table as these instruction can be considered as a subset of more than one category. within these tables, the sour ce operand is identified as ?src ?, the destination operand is ?dst? and a condition code is ?cc?. table 125. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract us ing extended addressing table 126. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 243 bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 127. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto- increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 128. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set register pointer table 126. bit manipulation instructions (continued) mnemonic operands instruction
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 244 stop ? stop mode wdt ? watchdog timer refresh table 129. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto-increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing table 130. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing table 128. cpu control instructions mnemonic operands instruction
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 245 xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 131. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 132. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic table 130. logical instructions (continued) mnemonic operands instruction
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 246 ez8 cpu instruction summary table 133 summarizes the ez8 cpu instructions . the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . srl dst shift right logical swap dst swap nibbles table 133. ez8 cpu instruction summary assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 * * * * 0 * 2 3 rir 13 2 4 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 * * * * 0 * 4 3 er im 19 4 3 add dst, src dst dst + src r r 02 * * * * 0 * 2 3 rir 03 2 4 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 * * * * 0 * 4 3 er im 09 4 3 table 132. rotate and shift instructions (continued) mnemonic operands instruction
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 247 and dst, src dst dst and src r r 52 - * * 0 - - 2 3 rir 53 2 4 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 - * * 0 - - 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ------ 1 2 bclr bit, dst dst[bit] 0 r e2 ------ 2 2 bit p, bit, dst dst[bit] p r e2 ------ 2 2 brk debugger break 00 - - - - - - 1 1 bset bit, dst dst[bit] 1 r e2 ------ 2 2 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 - - 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ------ 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ------ 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ------ 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ------ 2 6 da d6 3 3 ccf c ~c ef *----- 1 2 clr dst dst 00h r b0 ------ 2 2 ir b1 2 3 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 248 com dst dst ~dst r 60 - * * 0 - - 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * - - 2 3 rir a3 2 4 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * - - 3 3 rir1f a3 3 4 rr 1f a4 4 3 rir 1f a5 4 4 rim 1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * - - 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * - - 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x - - 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 - * * * - - 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 - * * * - - 2 5 irr 81 2 6 di irqctl[7] 0 8f ------ 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ------ 2 3 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 249 ei irqctl[7] 1 9f ------ 1 2 halt halt mode 7f ------ 1 2 inc dst dst dst + 1 r 20 - * * * - - 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 - * * * - - 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ****** 1 5 jp dst pc dst da 8d ------ 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ------ 3 2 jr dst pc pc + x da 8b ------ 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ------ 2 2 ld dst, rc dst src r im 0c-fc ------ 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 2 3 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 250 ldc dst, src dst src r irr c2 ------ 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 ------ 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ------ 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 ------ 2 9 irr ir 93 2 9 ldwx dst, src dst src er er 1f e8 ------ 54 ldx dst, src dst src r er 84 ------ 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ------ 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ------ 2 8 nop no operation 0f - - - - - - 1 2 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 251 or dst, src dst dst or src r r 42 - * * 0 - - 2 3 rir 43 2 4 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 - * * 0 - - 4 3 er im 49 4 3 pop dst dst @sp sp sp + 1 r 50 ------ 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ------ 3 2 push src sp sp ? 1 @sp src r 70 ------ 2 2 ir 71 2 3 im 1f 70 3 2 pushx src sp sp ? 1 @sp src er c8 ------ 3 2 rcf c 0 cf 0----- 1 2 ret pc @sp sp sp + 2 af ------ 1 4 rl dst r 90 ****-- 2 2 ir 91 2 3 rlc dst r 10 * * * * - - 2 2 ir 11 2 3 rr dst r e0 ****-- 2 2 ir e1 2 3 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 252 rrc dst r c0 * * * * - - 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 * * * * 1 * 2 3 rir 33 2 4 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 * * * * 1 * 4 3 er im 39 4 3 scf c 1 df 1----- 1 2 sra dst r d0 * * * 0 - - 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * - - 3 2 ir 1f c1 3 3 srp src rp src im 01 ------ 2 2 stop stop mode 6f ------ 1 2 sub dst, src dst dst ? src r r 22 * * * * 1 * 2 3 rir 23 2 4 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst dst ? src er er 28 * * * * 1 * 4 3 er im 29 4 3 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 253 swap dst dst[7:4] ? dst[3:0] r f0 x * * x - - 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 - * * 0 - - 2 3 rir 63 2 4 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 - * * 0 - - 4 3 er im 69 4 3 tm dst, src dst and src r r 72 - * * 0 - - 2 3 rir 73 2 4 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 - * * 0 - - 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ------ 2 6 wdt 5f ------ 1 2 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 254 xor dst, src dst dst xor src r r b2 - * * 0 - - 2 3 rir b3 2 4 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 - * * 0 - - 4 3 er im b9 4 3 flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 table 133. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 255 flags register the flags register contains the status inform ation regarding the most recent arithmetic, logical, bit manipulation or rotate and shift oper ation. the flags register contains six bits of status information that are set or clea red by cpu operations. four of the bits (c, v, z and s) can be tested for use with conditional jump instruc tions. two flags (h and d) cannot be tested and are used for binary-coded decimal (bcd) arithmetic. the two remaining bits, user flags (f1 and f2 ), are available as general-purpose status bits. user flags are unaffected by arithmetic operations and must be set or cleared by instructions. the user flags cannot be used with conditional jumps. they are undefined at initial power-up and are unaffected by reset. figure 57 displays the flags and their bit positions in the flags register. interrupts, the software trap (trap) instruction, and illegal instruction traps all write the value of the flags register to the stack. executing an interrupt return (iret) instruc- tion restores the value saved on th e stack into the flags register. u = undefined figure 57. flags register c z s v d h f2 f1 flags register bit 0 bit 7 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag user flags
ps019921-0308 ez8 ? cpu instruction set z8 encore! xp ? f64xx series product specification 256
ps019921-0308 opcode maps z8 encore! xp ? f64xx series product specification 257 opcode maps a description of the opcode map data and the abbreviations are provided in figure 58 and table 134 on page 258. figure 59 on page 259 and figure 60 on page 260 provide information on each of the ez8 tm cpu instructions. figure 58. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps019921-0308 opcode maps z8 encore! xp ? f64xx series product specification 258 table 134. opcode map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps019921-0308 opcode maps z8 encore! xp ? f64xx series product specification 259 figure 59. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.2 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1,2 atm
ps019921-0308 opcode maps z8 encore! xp ? f64xx series product specification 260 figure 60. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3,2 push im 5,4 ldwx er2,er1
ps019921-0308 packaging z8 encore! xp ? f64xx series product specification 261 packaging figure 61 displays the 44-pin low profile quad flat package (lqfp) available for the z8x1621, z8x2421, z8x3221, z8x4821, and z8x6421 devices. figure 61. 44-lead low-profile quad flat package (lqfp) a2 a a1 le c e he e l 0-7 b d hd detail a
ps019921-0308 packaging z8 encore! xp ? f64xx series product specification 262 figure 62 displays the 44-pin plastic lead chip carrier (plcc) package available for the z8x1621, z8x2421, z8x3221, z8x4821, and z8x6421 devices. figure 62. 44-lead plastic lead chip carrier package (plcc) figure 62 displays the 64-pin low-profile quad flat package (lqfp) available for the z8x1622, z8x2422, z8x3222, z8x4822, and z8x6422 devices. figure 63. 64-lead low-profile quad flat package (lqfp) 0.020/0.014 0.045/0.025 0.032/0.026 r 1.14/0.64 .028/.020 0.51/0.36 0.81/0.66 d2 e e1 3. dimension : mm 2. leads are coplanar within 0.004". 1. controlling dimension : inch notes: 17 18 inch 29 28 d d1 61 7 45 40 39 a1 a 0.71/0.51 1.321/1.067 0.052/0.042 e dim. from center to center of radii d/e 0.650 0.600 d1/e1 e d2 1.27 bsc 16.51 15.24 16.00 16.66 0.050 bsc 0.630 0.656 min 0.168 0.095 0.685 symbol a1 a millimeter 4.27 2.41 17.40 min 2.92 17.65 4.57 max 0.115 0.695 0.180 inch max m c a1 a2 a le e he e 0-7 l b hd d detail a
ps019921-0308 packaging z8 encore! xp ? f64xx series product specification 263 figure 64 displays the 68-pin plastic lead chip carrier (plcc) package available for the z8x1622, z8x2422, z8x3222, z8x4822, and z8x6422 devices. figure 64. 68-lead plastic lead chip carrier package (plcc)
ps019921-0308 packaging z8 encore! xp ? f64xx series product specification 264 figure 65 displays the 80-pin quad flat pack age (qfp) available for the z8x4823 and z8x6423 devices. figure 65. 80-lead quad-flat package (qfp) a2 e he 1 80 b detail a 0-10 l e 24 25 detail a hd d 65 64 40 41 17.70 he 18.15 .715 .697 .004" controlling dimensions : millimeter l e e c lead coplanarity : max .10 notes: 2. 0.80 bsc 0.70 13.90 1.10 14.10 .028 .043 .0315 bsc .547 .555 a1 d hd c b a2 symbol a1 19.90 23.70 0.13 2.60 0.30 0.10 20.10 24.15 0.20 0.38 2.80 0.45 millimeter min max .783 .933 .005 .791 .951 .008 .102 .012 .004 .110 .018 .015 inch min max
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 265 ordering information part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description z8f642x with 64 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f6421an020sc 64 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f6421vn020sc 64 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f6422ar020sc 64 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f6422vs020sc 64 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f6423ft020sc 64 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package extended temperature: ?40 c to +105 c Z8F6421AN020EC 64 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f6421vn020ec 64 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f6422ar020ec 64 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f6422vs020ec 64 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f6423ft020ec 64 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package automotive/industrial temperature: ?40 c to +125 c z8f6421an020ac 64 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f6421vn020ac 64 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f6422ar020ac 64 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f6422vs020ac 64 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f6423ft020ac 64 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 266 z8f482x with 48 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f4821an020sc 48 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f4821vn020sc 48 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f4822ar020sc 48 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f4822vs020sc 48 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f4823ft020sc 48 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package extended temperature: ?40 c to +105 c z8f4821an020ec 48 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f4821vn020ec 48 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f4822ar020ec 48 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f4822vs020ec 48 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f4823ft020ec 48 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package automotive/industrial temperature: ?40 c to +125 c z8f4821an020ac 48 kb 4 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f4821vn020ac 48 kb 4 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f4822ar020ac 48 kb 4 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f4822vs020ac 48 kb 4 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f4823ft020ac 48 kb 4 kb 60 24 4 12 1 1 2 qfp 80-pin package part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 267 z8f322x with 32 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f3221an020sc 32 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f3221vn020sc 32 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f3222ar020sc 32 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f3222vs020sc 32 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package extended temperature: ?40 c to 105 c z8f3221an020ec 32 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f3221vn020ec 32 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f3222ar020ec 32 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f3222vs020ec 32 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package automotive/industrial temperature: ?40 c to 125c z8f3221an020ac 32 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f3221vn020ac 32 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f3222ar020ac 32 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f3222vs020ac 32 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 268 z8f242x with 24 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f2421an020sc 24 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f2421vn020sc 24 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f2422ar020sc 24 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f2422vs020sc 24 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package extended temperature: ?40 c to 105 c z8f2421an020ec 24 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f2421vn020ec 24 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f2422ar020ec 24 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f2422vs020ec 24 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package automotive/industrial temperature: ?40 c to 125 c z8f2421an020ac 24 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f2421vn020ac 24 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f2422ar020ac 24 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f2422vs020ac 24 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 269 for technical and customer sup port, hardware and software de velopment tools, refer to the zilog ? website at www.zilog.com . the latest released version of zds can be downloaded from this website. z8f162x with 16 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f1621an020sc 16 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f1621vn020sc 16 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f1622ar020sc 16 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f1622vs020sc 16 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package extended temperature: ?40 c to +105 c z8f1621an020ec 16 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f1621vn020ec 16 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f1622ar020ec 16 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f1622vs020ec 16 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package automotive/industrial temperature: ?40 c to +125 c z8f1621an020ac 16 kb 2 kb 31 23 3 8 1 1 2 lqfp 44-pin package z8f1621vn020ac 16 kb 2 kb 31 23 3 8 1 1 2 plcc 44-pin package z8f1622ar020ac 16 kb 2 kb 46 24 4 12 1 1 2 lqfp 64-pin package z8f1622vs020ac 16 kb 2 kb 46 24 4 12 1 1 2 plcc 68-pin package z8f64200100kitg development kit zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isolated usb smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit note: replace c with g for lead-free packaging. part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 270 part number suffix designations z8 f 64 21 a n 020 s c environmental flow c = plastic standard g = lead free package temperature range (c) s = standard, 0 to 70 e = extended, ?40 to +105 a = automotive/industrial, ?40 to +125 speed 020 = 20 mhz pin count n = 44 pins r = 64 pins s = 68 pins t = 80 pins package a = lqfp f = qfp p = pdip v = plcc device type 21 = devices with 29 or 31 i/o lines, 23 interrupts, 3 timers and 8 adc channels 22 = devices with 46 i/o lines, 24 interrupts, 4 timers and 12 adc channels 23 = devices with 60 i/o lines, 24 interrupts, 4 timers and 12 adc channels memory size 64 kb flash, 4 kb ram 48 kb flash, 4 kb ram 32 kb flash, 2 kb ram 24 kb flash, 2 kb ram 16 kb flash, 2 kb ram memory type f = flash device family
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 271 example : part number z8f6421an020sc is an 8-bit microcontroller product in an lqfp package, using 44 pins, operating with a maximum 20 mhz external clock frequency over a 0 oc to +70 oc temperature range and bu ilt using the plastic-standard environmental flow.
ps019921-0308 ordering information z8 encore! xp ? f64xx series product specification 272
ps019921-0308 index z8 encore! xp ? f64xx series product specification 273 index symbols # 240 % 240 @ 240 numerics 10-bit adc 4 44-lead low-profile quad flat package 261 44-lead plastic lead chip carrier package 262 64-lead low-profile quad flat package 262 68-lead plastic lead chip carrier package 263 80-lead quad flat package 264 a absolute maximum ratings 211 ac characteristics 227 adc 242 architecture 171 automatic power-down 172 block diagram 172 continuous conversion 173 control register 175 control register definitions 175 data high byte register 176 data low bits register 176 dma control 174 electrical characteristics and timing 225 operation 172 single-shot conversion 173 adcctl register 175 adcdh register 176 adcdl register 176 adcx 242 add 242 add - extended addressing 242 add with carry 242 add with carry - extended addressing 242 additional symbols 240 address space 17 addx 242 analog signals 14 analog-to-digital converter (adc) 171 and 244 andx 244 arithmetic instructions 242 assembly language programming 237 assembly language syntax 238 b b 240 b 239 baud rate generator, uart 109 bclr 242 binary number suffix 240 bit 242 bit 239 clear 242 manipulation instructions 242 set 242 set or clear 242 swap 243 test and jump 245 test and jump if non-zero 245 test and jump if zero 245 bit jump and test if non-zero 245 bit swap 245 block diagram 3 block transfer instructions 243 brk 245 bset 242 bswap 243 , 245 btj 245 btjnz 245 btjz 245
ps019921-0308 index z8 encore! xp ? f64xx series product specification 274 c call procedure 245 capture mode 91 capture/compare mode 91 cc 239 ccf 243 characteristics, electrical 211 clear 244 clock phase (spi) 128 clr 244 com 244 compare 91 compare - extended addressing 242 compare mode 91 compare with carry 242 compare with carry - extended addressing 242 complement 244 complement carry flag 243 condition code 239 continuous conversion (adc) 173 continuous mode 90 control register definition, uart 110 control register, i2c 154 counter modes 90 cp 242 cpc 242 cpcx 242 cpu and peripheral overview 3 cpu control instructions 243 cpx 242 customer feedback form 287 customer feedback form 271 d da 239 , 242 data register, i2c 152 dc characteristics 213 debugger, on-chip 195 dec 242 decimal adjust 242 decrement 242 decrement and jump non-zero 245 decrement word 242 decw 242 destination operand 240 device, port availability 53 di 243 direct address 239 direct memory access controller 161 disable interrupts 243 djnz 245 dma address high nibble register 165 configuring dma0-1 data transfer 161 configuring for dma_adc data transfer 162 control of adc 174 control register 163 control register definitions 163 controller 5 dma_adc address register 167 dma_adc control register 168 dma_adc operation 162 end address low byte register 166 i/o address register 164 operation 161 start/current address low byte register 166 status register 169 dmaa_stat register 169 dmaactl register 168 dmaxctl register 163 dmaxend register 166 dmaxh register 165 dmaxi/o address (dmaxio) 165 dmaxio register 165 dmaxstart register 166 dst 240 e ei 243 electrical characteristics 211 adc 225 flash memory and timing 224 gpio input data sample timing 228 watch-dog timer 224 enable interrupt 243 er 239
ps019921-0308 index z8 encore! xp ? f64xx series product specification 275 extended addressing register 239 external pin reset 49 external rc oscillator 223 ez8 cpu features 3 ez8 cpu instruction classes 241 ez8 cpu instruction notation 238 ez8 cpu instruction set 237 ez8 cpu instruction summary 246 f fctl register 186 features, z8 encore! 1 first opcode map 259 flags 240 flags register 240 flash controller 4 option bit address space 191 option bit configuration - reset 191 program memory address 0001h 193 flash memory arrangement 180 byte programming 183 code protection 182 configurations 179 control register definitions 186 controller bypass 185 electrical characteristics and timing 224 flash control register 186 flash status register 186 frequency high and low byte registers 188 mass erase 185 operation 181 operation timing 182 page erase 184 page select register 187 fps register 187 fstat register 186 g gated mode 91 general-purpose i/o 53 gpio 4 , 53 alternate functions 54 architecture 53 control register definitions 56 input data sample timing 228 interrupts 56 port a-h address registers 57 port a-h alternate function sub-registers 59 port a-h control registers 58 port a-h data direction sub-registers 59 port a-h high drive enable sub-registers 60 port a-h input data registers 62 port a-h output control sub-registers 60 port a-h output data registers 62 port a-h stop mode recovery sub-registers 61 port availability by device 53 port input timing 228 port output timing 229 h h 240 halt 243 halt mode 51 , 243 hexadecimal number prefix/suffix 240 i i2c 4 10-bit address read transaction 150 10-bit address transaction 147 10-bit addressed slave data transfer format 147 10-bit receive data format 150 7-bit address transaction 145 7-bit address, reading a transaction 149 7-bit addressed slave data transfer format 144 , 145 , 146 7-bit receive data transfer format 149 baud high and low byte registers 156 , 157 , 159 c status register 153 control register definitions 152 controller 139 controller signals 13 interrupts 141
ps019921-0308 index z8 encore! xp ? f64xx series product specification 276 operation 140 sda and scl signals 141 stop and start conditions 143 i2cbrh register 156 , 157 , 159 i2cbrl register 157 i2cctl register 154 i2cdata register 153 i2cstat register 153 im 239 immediate data 239 immediate operand prefix 240 inc 242 increment 242 increment word 242 incw 242 indexed 239 indirect address prefix 240 indirect register 239 indirect register pair 239 indirect working register 239 indirect working register pair 239 infrared encoder/decoder (irda) 121 instruction set, ez8 cpu 237 instructions adc 242 adcx 242 add 242 addx 242 and 244 andx 244 arithmetic 242 bclr 242 bit 242 bit manipulation 242 block transfer 243 brk 245 bset 242 bswap 243 , 245 btj 245 btjnz 245 btjz 245 call 245 ccf 243 clr 244 com 244 cp 242 cpc 242 cpcx 242 cpu control 243 cpx 242 da 242 dec 242 decw 242 di 243 djnz 245 ei 243 halt 243 inc 242 incw 242 iret 245 jp 245 ld 244 ldc 244 ldci 243 , 244 lde 244 ldei 243 ldx 244 lea 244 load 244 logical 244 mult 242 nop 243 or 244 orx 244 pop 244 popx 244 program control 245 push 244 pushx 244 rcf 243 ret 245 rl 245 rlc 245 rotate and shift 245 rr 245 rrc 245 sbc 242 scf 243
ps019921-0308 index z8 encore! xp ? f64xx series product specification 277 sra 245 srl 246 srp 243 stop 244 sub 242 subx 242 swap 246 tcm 243 tcmx 243 tm 243 tmx 243 trap 245 watch-dog timer refresh 244 xor 245 xorx 245 instructions, ez8 classes of 241 interrupt control register 75 interrupt controller 5 , 63 architecture 63 interrupt assertion types 66 interrupt vectors and priority 66 operation 65 register definitions 67 software interrupt assertion 66 interrupt edge select register 74 interrupt port select register 74 interrupt request 0 register 67 interrupt request 1 register 68 interrupt request 2 register 69 interrupt return 245 interrupt vector listing 63 interrupts not acknowledge 141 receive 141 spi 131 transmit 141 uart 107 introduction 1 ir 239 ir 239 irda architecture 121 block diagram 121 control register definitions 124 operation 121 receiving data 122 transmitting data 122 iret 245 irq0 enable high and low bit registers 70 irq1 enable high and low bit registers 71 irq2 enable high and low bit registers 72 irr 239 irr 239 j jp 245 jump, conditional, relative, and relative conditional 245 l ld 244 ldc 244 ldci 243 , 244 lde 244 ldei 243 , 244 ldx 244 lea 244 load 244 load constant 243 load constant to/from program memory 244 load constant with auto-increment addresses 244 load effective address 244 load external data 244 load external data to/fro m data memory and auto- increment addresses 243 load external to/from data memory and auto-incre- ment addresses 244 load instructions 244 load using extended addressing 244 logical and 244 logical and/extended addressing 244 logical exclusive or 245 logical exclusive or/extended addressing 245 logical instructions 244 logical or 244 logical or/extended addressing 244
ps019921-0308 index z8 encore! xp ? f64xx series product specification 278 low power modes 51 lqfp 44 lead 261 64 lead 262 m master interrupt enable 65 master-in, slave-out and-in 127 memory program 17 miso 127 mode capture 91 capture/compare 91 continuous 90 counter 90 gated 91 one-shot 90 pwm 90 modes 91 mult 242 multiply 242 multiprocessor mode, uart 105 n nop (no operation) 243 not acknowledge interrupt 141 notation b 239 cc 239 da 239 er 239 im 239 ir 239 ir 239 irr 239 irr 239 p 239 r 239 r 239 ra 239 rr 239 rr 239 vector 239 x 239 notational shorthand 239 o ocd architecture 195 auto-baud detector/generator 198 baud rate limits 198 block diagram 195 breakpoints 199 commands 200 control register 205 data format 197 dbg pin to rs-232 interface 196 debug mode 197 debugger break 245 interface 195 serial errors 198 status register 206 timing 230 ocd commands execute instruction (12h) 204 read data memory (0dh) 203 read ocd control register (05h) 201 read ocd revision (00h) 201 read ocd status register (02h) 201 read program counter (07h) 202 read program memory (0bh) 203 read program memory crc (0eh) 203 read register (09h) 202 step instruction (10h) 204 stuff instruction (11h) 204 write data memory (0ch) 203 write ocd control register (04h) 201 write program counter (06h) 201 write program memory (0ah) 202 write register (08h) 202 on-chip debugger 5 on-chip debugger (ocd) 195 on-chip debugger signals 15 on-chip oscillator 207
ps019921-0308 index z8 encore! xp ? f64xx series product specification 279 one-shot mode 90 opcode map abbreviations 258 cell description 257 first 259 second after 1fh 260 operational description 99 or 244 ordering information 265 orx 244 oscillator signals 14 p p 239 packaging lqfp 44 lead 261 64 lead 262 plcc 44 lead 262 68 lead 263 qfp 264 part number description 270 part selection guide 2 pc 240 peripheral ac and dc el ectrical characteristics 222 phase=0 timing (spi) 129 phase=1 timing (spi) 130 pin characteristics 15 plcc 44 lead 262 68-lead 263 polarity 239 pop 244 pop using extended addressing 244 popx 244 port availability, device 53 port input timing (gpio) 228 port output timing, gpio 229 power supply signals 15 power-down, automatic (adc) 172 power-on and voltage brown-out 222 power-on reset (por) 47 program control instructions 245 program counter 240 program memory 17 push 244 push using extended addressing 244 pushx 244 pwm mode 90 pxaddr register 57 pxctl register 58 q qfp 264 r r 239 r 239 ra register address 239 rcf 243 receive 10-bit data format (i2c) 150 7-bit data transfer format (i2c) 149 irda data 122 receive interrupt 141 receiving uart data-interrupt-driven method 104 receiving uart data-polled method 103 register 136 , 165 , 239 adc control (adcctl) 175 adc data high byte (adcdh) 176 adc data low bits (adcdl) 176 baud low and high byte (i2c) 156 , 157 , 159 baud rate high and low byte (spi) 138 control (spi) 133 control, i2c 154 data, spi 133 dma status (dmaa_stat) 169 dma_adc address 167 dma_adc control dmaactl) 168 dmax address high nibble (dmaxh) 165 dmax control (dmaxctl) 163 dmax end/address low byte (dmaxend) 166 dmax start/current address low byte register
ps019921-0308 index z8 encore! xp ? f64xx series product specification 280 (dmaxstart) 166 flash control (fctl) 186 flash high and low byte (ffreqh and fre- eql) 188 flash page select (fps) 187 flash status (fstat) 186 gpio port a-h address (pxaddr) 57 gpio port a-h alternate function sub-registers 59 gpio port a-h control address (pxctl) 58 gpio port a-h data direction sub-registers 59 i2c baud rate high (i2cbrh) 156 , 157 , 159 i2c control (i2cctl) 154 i2c data (i2cdata) 153 i2c status 153 i2c status (i2cstat) 153 i2cbaud rate low (i2cbrl) 157 mode, spi 136 ocd control 205 ocd status 206 spi baud rate high byte (spibrh) 138 spi baud rate low byte (spibrl) 138 spi control (spictl) 134 spi data (spidata) 133 spi status (spistat) 135 status, i2c 153 status, spi 135 uartx baud rate high byte (uxbrh) 117 uartx baud rate low byte (uxbrl) 117 uartx control 0 (uxctl0) 113 , 116 uartx control 1 (uxctl1) 114 uartx receive data (uxrxd) 111 uartx status 0 (uxstat0) 111 uartx status 1 (uxstat1) 113 uartx transmit data (uxtxd) 110 watchdog timer control (wdtctl) 96 watchdog timer reload high byte (wdth) 98 watchdog timer reload low byte (wdtl) 98 watchdog timer reload upper byte (wdtu) 98 register file 17 register file address map 21 register pair 239 register pointer 240 reset and stop mode characteristics 45 carry flag 243 controller 5 sources 46 ret 245 return 245 rl 245 rlc 245 rotate and shift instructions 245 rotate left 245 rotate left through carry 245 rotate right 245 rotate right through carry 245 rp 240 rr 239 , 245 rr 239 rrc 245 s sbc 242 scf 243 sda and scl (irda) signals 141 second opcode map after 1fh 260 serial clock 127 serial peripheral interface (spi) 125 set carry flag 243 set register pointer 243 shift right arithmetic 245 shift right logical 246 signal descriptions 13 single-shot conversion (adc) 173 sio 5 slave data transfer formats (i2c) 147 slave select 128 software trap 245 source operand 240 sp 240 spi architecture 125 baud rate generator 132 baud rate high and low byte register 138 clock phase 128 configured as slave 126
ps019921-0308 index z8 encore! xp ? f64xx series product specification 281 control register 133 control register definitions 133 data register 133 error detection 131 interrupts 131 mode fault error 131 mode register 136 multi-master operation 130 operation 126 overrun error 131 signals 127 single master, multiple slave system 126 single master, single slave system 125 status register 135 timing, phase = 0 129 timing, phase=1 130 spi controller signals 13 spi mode (spimode) 136 spibrh register 138 spibrl register 138 spictl register 134 spidata register 133 spimode register 136 spistat register 135 sra 245 src 240 srl 246 srp 243 stack pointer 240 status register, i2c 153 stop 244 stop mode 51 , 244 stop mode recovery sources 49 using a gpio port pin transition 50 using watchdog timer time-out 50 sub 242 subtract 242 subtract - extended addressing 242 subtract with carry 242 subtract with carry - extended addressing 242 subx 242 swap 246 swap nibbles 246 symbols, additional 240 system and core resets 46 t tcm 243 tcmx 243 technical support 287 test complement under mask 243 test complement under mask - extended addressing 243 test under mask 243 test under mask - extended addressing 243 timer signals 14 timers 5 , 77 architecture 77 block diagram 78 capture mode 82 , 91 capture/compare mode 85 , 91 compare mode 83 , 91 continuous mode 79 , 90 counter mode 80 counter modes 90 gated mode 84 , 91 one-shot mode 78 , 90 operating mode 78 pwm mode 81 , 90 reading the timer count values 86 reload high and low byte registers 87 timer control register definitions 86 timer output signal operation 86 timers 0-3 control 0 registers 89 control 1 registers 90 high and low byte registers 86 , 88 tm 243 tmx 243 transmit irda data 122 transmit interrupt 141 transmitting uart data-interrupt-driven method 102 transmitting uart data-polled method 101 trap 245
ps019921-0308 index z8 encore! xp ? f64xx series product specification 282 u uart 4 architecture 99 asynchronous data format without/with parity 101 baud rate generator 109 baud rates table 118 control register definitions 110 controller signals 14 data format 100 interrupts 107 multiprocessor mode 105 receiving data using interrupt-driven method 104 receiving data using the polled method 103 transmitting data using the interrupt-driven method 102 transmitting data using the polled method 101 x baud rate high and low registers 116 x control 0 and control 1 registers 113 x status 0 and status 1 registers 111 , 112 uxbrh register 117 uxbrl register 117 uxctl0 register 113 , 116 uxctl1 register 114 uxrxd register 111 uxstat0 register 111 uxstat1 register 113 uxtxd register 110 v vector 239 voltage brownout reset (vbr) 47 w watchdog timer approximate time-out delay 94 cntl 48 control register 96 refresh 94 electrical characteristics and timing 224 interrupt in normal operation 94 interrupt in stop mode 94 refresh 244 reload unlock sequence 95 reload upper, high and low registers 97 reset 48 reset in normal operation 95 reset in stop mode 95 time-out response 94 wdtctl register 96 wdth register 98 wdtl register 98 working register 239 working register pair 239 wtdu register 98 x x 239 xor 245 xorx 245 z z8 encore! block diagram 3 features 1 introduction 1 part selection guide 2
ps019921-0308 customer support z8 encore! xp ? f64xx series product specification 283 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questi ons, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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